Fabrication technique for Si single-electron transistor operatingat room temperature

A Si single electron transistor (SET) was fabricated by converting a one-dimensional Si wire on a SIMOX substrate into a small Si island with a tunnelling barrier at each end by means of pattern-dependent oxidation. With this structure, the total capacitance was reduced to ~2aF, which enabled conductance oscillation of the SET at room temperature     

纳米器件与单电子晶体管

报道了一种非常重要的纳米器件———单电子晶体管,介绍了它的原理、基本特性、制备方法及其集成,着重分析讨论了两种新型的单电子晶体管即波导型单电子晶体管和点接触栅型单电子晶体管。     

Macromodeling of single-electron transistors for efficient circuitsimulation

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations     

A new SIMPLORER model for single-electron transistors

In the first part of this paper, we present simulations of single-electron transistor (SET) output characteristic using Maple. Typical SET I–V characteristics and charge energies curves are presented by developing Maple programs. In the second part of this work, we develop a new model without considering quantum effects using the superposition theorem, transfer function and Laplace transformer. Finally, we propose a new bloc using SIMPLORER 7.0 simulator to modulate quantum effects in the SET island. This model is based on a parallel analog–digital converter.     

Analog-to-digital converter based on single-electron tunneling transistors

A novel single-electron tunneling transistors (SETTs) based analog-to-digital converter (ADC) is proposed in this paper. The scheme we propose fully utilizes Coulomb oscillation effect, can properly operate at T>0 K, and only a capacitive divider (built with 2n-2 capacitors) and n pairs of complementary SETTs are required for an n-bit ADC implementation. When compared with other state-of-the-art SET based ADCs our method provides the most compact solution measured in terms of circuit elements and has a potential advantage in terms of conversion speed. To illustrate the operation of the proposed scheme, a 4-bit ADC is demonstrated at 10K by means of simulation.     

纳米器件与单电子晶体管(续)

6单电子晶体管的集成单电子晶体管的集成化将依赖于各元器件的无线耦合[3],这与传统的大规模集成电路原理不同.基于这种单电子器件的集成原理,Nakazato等人[4,5]实现了有存储功能的单电子存储器和单电子逻辑电路.它们通过单电子晶体管间的隧穿耦合和电容耦合来实现单电子器件的集成.     

基于单电子晶体管的数字滤波器硬件实现

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。在讨论数字滤波器硬件实现原理基础上，由这三个单元电路实现了一个二阶IIR滤波器。SET的SPICE宏模型验证了设计的正确性。     

Silicon single-electron transistors with sidewall depletion gatesand their application to dynamic single-electron transistor logic

Novel single-electron transistors (SETs) with side-wall depletion gates on a silicon-on-insulator nanometer-scale wire are proposed and fabricated, using the combination of the conventional lithography and process technology. Clear Coulomb oscillation originated from the two electrically induced tunnel junctions and the single Si island between them is observed at 77 K. The island size dependence of the electrical characteristics shows the good controllability and reproducibility of the proposed fabrication method. Furthermore, the device characteristics are immune to gate bias conditions, and the position of Coulomb oscillation peak is controlled by the sidewall depletion gate voltage, without the additional gate electrode. Based on the current switching by sidewall gate voltage, the basic operation of the dynamic four-input multifunctional SET logic circuit is demonstrated at 10 K. The proposed SET offers the feasibility of the device design and optimization for SET logic circuits, in that its device parameters and circuit parameters are controllable by the conventional VLSI technology     

Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors

In this paper, various circuit and system level design challenges for nanometer-scale devices and single-electron transistors are discussed, with an emphasis to the functional robustness and fault tolerance point of view. A set of general guidelines is identified for the design of very high-density digital systems using inherently unreliable and error-prone devices. The fundamental principles of a highly regular, redundant, and scalable design approach based on fixed-weight neural networks and multiple-valued logic are presented. It is demonstrated that the proposed design technique offers significantly improved immunity to permanent and transient faults occurring at the transistor level, and that it results in graceful degradation of circuit performance in response to device failures.     

Complimentary single-electron/hole action of nanoscale SOI CMOS transistors

We propose a new device structure for room-temperature single-electron/hole transistors based on nanosize narrow-width fully depleted silicon-on-insulator (SOI) CMOS transistors. The floating body of SOI MOSFETs can become a Coulomb island, whose single charging energy is more than 30 meV, as the gate length and width of MOSFETs is less than 10 nm. As SOI MOSFETs are biased at accumulation, single-electron, or hole tunnels, are sent, one by one, from the source to the floating body and then to the drain via Zener tunneling process. N-channel SOI MOSFETs can have the functions of single-electron transistors (n-SETs) while p-channel MOSFETs can have the functions of single-hole transistors (p-SETs). SOI MOSFETs still behave as typical MOSFETs when biased at inversion. There is a gate voltage margin of 0.9 V to separate Coulomb blockade oscillations from CMOS normal operation.     

点接触平面栅型硅单电子晶体管

设计了点接触平面栅型硅单电子晶体管,利用自对准技术实现了点接触平面栅,并通过给平面栅施加偏压实现了量子点。讨论了点接触平面栅型单电子晶体管与其通道宽度和平面栅上电压的关系。对一个具有70nm宽通道的器件,先在其表面栅上施加很小的正偏压,然后又在其平面栅上施加负偏压耗尽通道,最终的研究结果显示在通道中形成了单个量子点。     

Amorphous Si/Si heterojunction microwave transistors

Because the emitter-base junctions of amorphous Si/Si heterojunction bipolar transistors (HBTs) with a conventional structure are inside the amorphous Si (a-Si) layer, their high-frequency performance is limited due to very low electron velocity in a-Si. An improved structure, the two-dimensional-electron-gas (2DEG) emitter structure, is proposed to overcome these problems, and a-Si/Si HBTs with good high-frequency performance are fabricated. Their low-temperature fabrication technology can be extended to other III-V-compound HBTs     

Self-assembled Ge/Si dots for faster field-effect transistors

Self-assembled and coherently strained germanium nanostructured dots are grown on prepatterned Si substrates along ordered lines. These precisely aligned nanocrystals are proposed to make up the central unit of a dot-based field-effect transistor (DotFET). The strain-induced band edge splitting and the inherently smaller effective masses of charge carriers in Ge/Si dots promise faster transistors than are possible for conventional pure Si devices. Thick relaxed buffer layers-mandatory for any existing high-speed SiGe field-effect devices-are no longer required. The DotFET is straight-forward, defect-free, and fully compatible with current complementary metal-oxide-semiconductor (CMOS) technology     

Design and simulation of octal-to-binary encoder using capacitive single-electron transistors (C-SETs)

This paper presents an octal-to-binary encoder that is designed using capacitive single-electron transistors (C-SETs). The design parameters are calculated by considering each C-SET as a switching device in pull-up configuration. Logic circuit is based on voltage state logic. The designed circuit was simulated using SIMON 2.0, which is based on Monte Carlo and master equation (MC-ME) methods. The simulation results verify the operation of octal-to-binary encoder.     

High-performance Si/SiGe n-type modulation-doped transistors

Enhancement-mode Si/SiGe n-type modulation-doped transistors with a 0.5-μm-length T-gate have been fabricated. Peak transconductances of 390 mS/mm at room temperature and 520 mS/mm at 77 K have been achieved. These high values are attributable to a combination of the high quality of the material used, having a room temperature mobility of 2600 cm²/V-s at an electron sheet concentration of 1.5×10¹² cm², and an optimized layer design that minimizes the parasitic series resistance and the gate-to-channel distance     

Fabrication of poly(3-hexylthiophene) nanowires for high-mobility transistors

Presented here is a novel and efficient method used to improve carrier mobilities of poly(3-hexylthiophene) (P3HT)-based organic field effect transistors by means of nanowire formation. The treatment, termed solvation, consists of depositing a small quantity of a solvent directly on top of a previously deposited semiconducting film, and allowing the solvent to evaporate slowly. Such treatment results in an increase of the saturation mobility by more than one order of magnitude, from 1.3 × 10⁻³ up to 3.4 × 10⁻² cm²/Vs, while devices preserve their high ON/OFF ratio of ∼10⁴. The atomic force and scanning electron microscopy studies show that solvated P3HT layers develop a network of nanowires, which exhibit increased degree of structural order, as demonstrated by micro Raman spectroscopy. The time-of-flight photoconductivity studies suggest that higher hole mobility stems from a reduced energy disorder of the transporting states in these structures.     

Fabrication of gate-all-around transistors using metal inducedlateral crystallization

Gate-all-around transistor (GAT) is demonstrated. The device can be fabricated on either a bulk silicon wafer or on the top of any device layers. The fabrication process used a new technique called metal-induced-lateral-crystallization (MILC) to recrystallize amorphous silicon to form large silicon grains in the active area. Using this technique, the transistor performance is comparable to a SOI MOSFET. Compared with the single-gate thin film transistor (SGT) and solid phase crystallization (SPC) devices, the MILC GAT has lower subthreshold slope, lower threshold voltage, higher transconductance and nearly double drive current, The impact of short channel length was investigated     

基于介电泳技术制备SiC纳米线薄膜晶体管

本文从理论和实验两方面,研究了介电泳技术中SiC纳米线溶剂的选择。从介电泳力、介电泳力矩、溶剂的挥发性和毒性角度分析,发现异丙醇是合适的SiC纳米线溶剂。以异丙醇作为溶剂,利用介电泳技术实现了SiC纳米线的定向排列,并得到纳米线薄膜。SiC纳米线溶液浓度分别为0.1μg/μL,0.3μg/μL, 0.5μg/μL时,得到定向排列纳米线的密度分别为 2/μm,4/μm,6/μm。并且利用密度为6/μm的SiC纳米线薄膜制备了晶体管,该晶体管的迁移率为13.4 cm2/V?s。     

高性能钆铝锌氧薄膜晶体管的制备

本文研究并制备了钆铝锌氧薄膜和以钆铝锌氧为有源层的薄膜晶体管。钆铝锌氧薄膜材料的光致发光光谱和透过率说明钆铝锌氧薄膜在透明显示方向的应用潜力。透射电子显微镜揭示了钆铝锌氧薄膜的非晶态微观结构。钆铝锌氧薄膜晶体管显示了良好的转移特性和输出特性。器件开关比大于10~5、饱和迁移率约为10cm~2·V~(-1)·s~(-1)。实验结果表明,钆铝锌氧薄膜可用作氧化物薄膜晶体管的有源层材料;钆铝锌氧薄膜晶体管可作为像素电路的驱动器件。     

Schottky base edge leakage in Si permeable-base transistors

The base leakage/breakdown mechanism in the Si permeable-base transistor (SiPBT) is related to the radius of curvature of the depletion region directly below the edge of the metal semiconductor interface. The unique geometry of the SiPBT illustrates the edge breakdown phenomena. As higher reverse bias is applied to the base-collector junction, the adjacent depletion regions in the grating fuse and the exposed edge perimeter will vary to form a kink in the IV characteristics. The grating will self-guard. As the SiPBT design parameters are scaled to finer gratings, the carrier concentration under the base must increase to maintain permeable-base transistor action. These fine-period SiPBT's will also self-guard within the grating region.