On circuit techniques to improve noise immunity of CMOS dynamic logic

Dynamic CMOS logic circuits are widely employed in high-performance VLSI chips in pursuing very high system performance. However, dynamic CMOS gates are inherently less resistant to noises than static CMOS gates. With the increasing stringent noise requirement due to aggressive technology scaling, the noise tolerance of dynamic circuits has to be first improved for the overall reliable operation of VLSI chips designed using deep submicron process technology. In the literature, a number of design techniques have been proposed to enhance the noise tolerance of dynamic logic gates. An overview and classification of these techniques are first presented in this paper. Then, we introduce a novel noise-tolerant design technique using circuitry exhibiting a negative differential resistance effect. We have demonstrated through analysis and simulation that using the proposed method the noise tolerance of dynamic logic gates can be improved beyond the level of static CMOS logic gates while the performance advantage of dynamic circuits is still retained. Simulation results on large fan-in dynamic CMOS logic gates have shown that, at a supply voltage of 1.6 V, the input noise immunity level can be increased to 0.8 V for about 10% delay overhead and to 1.0 V for only about 20% delay overhead.     

模拟电路噪声的来源和消除

模拟电路噪声的消除更多地依赖于经验而非科学依据。设计人员经常遇到的情况是电路的模拟硬件部分设计出来以后,却发现电路中的噪声太大,而不得不重新进行设计和布线。这种“试试看”的设计方法在几经周折之后最终也能获得成功。不过,避免噪声问题的更好方法是在设计初期进行决策时就遵循一些基本的设计准则,并运用与噪声相关的基本原理等知识。     

Analog CMOS realization of fuzzy logic membership functions

The design of a monolithic CMOS analog function synthesizer based on a current-mode algorithm and its application in fuzzy membership function synthesis is presented. The proposed circuits require only one reference current, independently of the course or the number of implemented functions. The networks are temperature and technology insensitive. Other features are a small chip area and a simple design process for any arbitrary functions. Matching considerations allow a prediction of the available approximation accuracy. Theoretical evaluations are validated by measurements of several membership functions fabricated in an experimental 1.0-μm CMOS technology     

Programmable logic array optimization techniques

The programmable logic array (PLA) has become a convenient logic element in digital system design. This paper attempts to solve three problems : (i) minimization of the number of input variables (pins) of the functions, (ii) minimization of the number of product. terms (AND-gates) needed, and (iii) the sufficient conditions under which a variable can lie eliminated without, increasing the number of product terms needed by a function. A branch-and-bound algorithm and a ‘ greedy ’ heuristic are developed for the minimization problems.     

Tabular techniques for OR-coincidence logic

The map folding method for the conversion between Boolean expression and COC expansions is analyzed. Based on it, the tabular techniques are proposed for the conversion between Boolean expression and COC expansion and for the derivation of GOC expansions with fixed polarities. The Fast Tabular Technique （FTT） for the conversion from the Boolean expression to the GOC expansion with the required polarity is also proposed. The simulative result shows this FTT is faster than others in references because of its inherent parallelism.     

Analog synthesis of nonlinear functions based on fuzzy logic

A circuit for the analog implementation of nonlinear functions has been designed. It is based on the fuzzy-logic paradigm mapped into a modular architecture. The basic building blocks rely on the large-signal characteristic of MOS differential pairs to design bell-shaped basis functions and combine them with the center-of-gravity method. The actual input/output (I/O) characteristics are defined by applying proper voltage levels to the high-impedance input nodes of each module. Both a field-programmable processor, where the programming configuration is stored in a digital RAM, and a tool for generating the layout of dedicated circuits, where this connection is hardwired, have been designed using a CMOS 0.7 μm n-well technology. A software layer computes the programming values which allow the circuit response to approximate the target I/O relationship. Experiments show that the approximation accuracy is in the range of a few percent r.m.s. of the circuit output range. The application of the system to the synthesis of a nonlinear control law for a DC-DC power converter is discussed     

Estimation of the noise immunity of immitance logic elements

The noise immunity of immitance logic elements (ILEs) realized on the basis of a transistor generalized immitance converter (GIC) is analytically estimated. It is shown that this estimate is determined by the effect of static interferences (temperature and supply voltage changes), high-frequency interferences (reference oscillation power and frequency changes), and immitance interferences (changes of the real and imaginary components of the immitance to be converted and changes of internal interferences related with the GIC potential instability). It is suggested to use the relative noise immunity coefficients for the immitance levels of logic 0-γ _C , and logic 1-γ _L , for analytical estimation of the ILE noise immunity. The admissible range of variation of these immitance levels are 0 < γ _C < 1 and 0 < γ _L < 1. The noise immunity is quantitatively estimated. As a result, it is found that, within the reference frequency 0.4–1.5 GHz, an ILE’s reserve of the noise immunity to the instability of the imaginary component of the high-Q input immitance exceeds 80% and that the noise immunity reserve is reduced by no more than 5% when the supply voltage changes by 30% and when the temperature changes by 40%.     

Analog circuit fault diagnosis based on noise measurement

In this paper, an analog circuit fault diagnosis method using a noise measurement and analysis approach is suggested. Compared to the conventional circuit fault diagnosis methods, this method can discover hidden and early circuit fault caused by the device defects. Since circuit fault diagnosis is more difficult than device-defect detection, in this paper the circuit output noise calculation, the comparison between the normal and failure conditions and the circuit fault diagnosis method have been discussed. Finally, an example of an active filter circuit fault diagnosis has been given by using this method.     

Crosstalk noise reduction in synthesized digital logic circuits

As CMOS technology scales into the deep submicrometer regime, digital noise is becoming a metric of importance comparable to area, timing, and power, for analysis and design of CMOS VLSI systems. Noise has two detrimental effects in digital circuits: First, it can destroy logical information carried by a circuit net. Second, it causes delay uncertainty: Non critical paths might become critical because of noise. As a result, circuit speed becomes limited by noise, primarily because of capacitive coupling between wires. Most design approaches address the crosstalk noise problem at the layout generation stage, or via postlayout corrections. With continued scaling, too many circuit nets require corrections for noise, causing a design convergence problem. This work suggests to consider noise at the gate-level netlist generation stage. The paper presents a simplified analysis of on-chip crosstalk models, and demonstrates the significance of crosstalk between local wires within synthesized circuit blocks. A design flow is proposed for automatically synthesizing CMOS circuits that have improved robustness to noise effects, using standard tools, by limiting the range of gate strengths available in the cell library. The synthesized circuits incur a penalty in area/power, which can be partially recovered in a single postlayout corrective iteration. Results of design experiments indicate that delay uncertainty is the most important noise-related concern in synthesized static CMOS logic. Using a standard synthesis methodology, critical path delay differences up to 18% of the clock cycle time have been observed in functional blocks of microprocessor circuits. By using the proposed design flow, timing uncertainty was reduced to below 3%, with area and power penalties below 20%.     

Static and dynamic noise margins of logic circuits

Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example.     

Analog circuits optimization based on evolutionary computation techniques

This paper presents a new design automation tool, based on a modified genetic algorithm kernel, in order to improve efficiency on the analog IC design cycle. The proposed approach combines a robust optimization with corner analysis, machine learning techniques and distributed processing capability able to deal with multi-objective and constrained optimization problems. The resulting optimization tool and the improvement in design productivity is demonstrated for the design of CMOS operational amplifiers.     

Novel techniques for memristive multifunction logic design

We present novel techniques for realising reliable low overhead logic functions and more complex systems based on the switching characteristics of memristors. Firstly, we show that memristive circuits have inherent properties for realising multiple valued MIN-MAX operations over the post algebra. We then present an efficient hybrid 1T-4M logic architecture for dual XOR/AND and XNOR/OR functionality, which can be seamlessly integrated with the existing CMOS technology. Although memristors are usually considered to operate at lower frequencies, however, recent advances in technology show their potentiality at high frequencies. To this end, we also explore the effects of high frequencies on their performance and thereby propose reliable high frequency design techniques based on our 1T-4M architectures. Experimental results, based on the design of full adders and multipliers over GF, show that the proposed designs require significantly lower power and overhead while maintaining reliable performance at low as well as at high frequencies compared to the existing techniques.     

C-testable design techniques for iterative logic arrays

A design-for-testability (DFT) approach for VLSI iterative logic arrays (ILA's) is proposed, which results in a small constant number of test patterns. Our technique applies to arrays with an arbitrary dimension, and to arrays with various connection types, e.g., hexagonal or octagonal ones. Bilateral ILA's are also discussed. The DFT technique makes general ILA's C-testable by using a truth-table augmentation approach. We propose an output-assignment algorithm for minimizing the hardware overhead. We give a CMOS systolic array multiplier as an example, and show that an overhead of no more than 5.88% is sufficient to make it C-testable, i.e., 100% single cell-fault testable with only 18 test patterns regardless of the word length of the multiplier. Our technique guarantees that the test set is easy to generate. Its corresponding built-in-self-test structures are also very simple     

A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic

Differential cascode voltage switch (DCVS) logic is a CMOS circuit technique that has potential advantages over conventional NAND/NOR logic in terms of circuit delay, layout density, power dissipation, and logic flexibility. A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques. The parameters compared are: input gate capacitance, number of transistors required, propagation delay time, and average power dissipation. In the static case, DCVS appears to be superior to full CMOS in regards to input capacitance and device count but inferior in regards to power dissipation. The speeds of the two technologies are similar. In the dynamic case, DCVS can be faster than more conventional CMOS dynamic logic, but only at the expense of increased device count and power dissipation.     

将射频放大器噪声系数减至最小的基本技术与方法

低噪声微波晶体管通常要求具有最小的噪声系数及相应的增益(一般O.5～1.5分贝,小于晶体管的最大有效增益).这可通过调节放大器,牺牲一点噪声系数来获得最佳的性能.     

Further improve circuit partitioning using GBAW logic perturbation techniques

Efficient circuit partitioning is becoming more and more important as the size of modern circuits keeps increasing. Conventionally, circuit partitioning is solved without altering the circuit by modeling the circuit as a hypergraph for the ease of applying graph algorithms. However, there is room for further improvement on even optimal hypergraph partitioning results, if logic information can be applied for circuit perturbation. Such logic transformation based partitioning techniques are relatively less addressed. In this paper, we present a powerful multiway partitioning technique which applies efficient logic rewiring techniques for further improvement over already superior hypergraph partitioning results. The approach can integrate with any graph partitioner. We perform experiments on two-, three-, and four-way partitionings for MCNC benchmark circuits whose physical and logical information are both available. Our experimental results show that this partitioning approach is very powerful. For example, it can achieve a further 12.3% reduction in cut size upon already excellent pure graph partitioner (hMetis) results on two-way partitioning with an area penalty of only 0.34%. The outperforming results demonstrate the usefulness of this new partitioning technique.