A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.     

A novel fabrication method for the nanoscale tunneling field effect transistor

Tunneling Field Effect Transistors (TFETs) are considered as a candidate for low power applications. However, most of TFETs have been researched on only for long channels due to the misalignment problem that occurs during the source/drain doping process in device fabrication. Thus, a new method is proposed for the fabrication of TFETs in nanoscale regions. This proposed fabrication process does not need an additional mask to define the source/drain regions, and makes it possible to form a self-aligned source/drain doping process. In addition, through TCAD simulation, the electrical characteristics of a TFET with dopant engineering and a rounded gate edge shape for a higher on/off current ratio were investigated. As a result, the TFET showed the properties of a larger on-current, a lower average subthreshold swing (58.5 mV/dec), and a 30-fold smaller leakage current compared to the conventional TFET The TFET with dopant engineering and a rounded gate edge shape can also be fabricated simply through the proposed fabrication process.     

Performance simulation of nanoscale silicon rod field-effect transistor logic

We have simulated the behavior of a rod shaped nanoscale ring-gated field-effect transistor (RG-FET) using the PISCES-IIb semiconductor drift-diffusion solver. The results from these simulations are used by a customized SPICE 3f5 kernel to simulate several simple logic gates. The usefulness of this kind of transistor is examined within the context of a self-assembling fabrication technique that we outline.     

Nonphotolithographic nanoscale memory density prospects

Technologies are now emerging to construct molecular-scale electronic wires and switches using bottom-up self-assembly. This opens the possibility of constructing nanoscale circuits and memories where active devices are just a few nanometers square and wire pitches may be on the order of ten nanometers. The features can be defined at this scale without using photolithography. The available assembly techniques have relatively high defect rates compared to conventional lithographic integrated circuits and can only produce very regular structures. Nonetheless, with proper memory organization, it is reasonable to expect these technologies to provide memory densities in excess of 10/sup 11/ b/cm/sup 2/ with modest active power requirements under 0.6 W/Tb/s for random read operations.     

A molecular dynamics simulation study on trapping ions in a nanoscale Paul trap

We found by molecular dynamics simulations that a low energy ion can be trapped effectively in a nanoscale Paul trap in both vacuum and aqueous environments when appropriate AC/DC electric fields are applied to the system. Using the negatively charged chlorine ion as an example, we show that the trapped ion oscillates around the center of the nanotrap with an amplitude dependent on the parameters of the system and applied voltages. Successful trapping of the ion within nanoseconds requires an electric bias of GHz frequency, in the range of hundreds of mV. The oscillations are damped in the aqueous environment, but polarization of water molecules requires the application of a higher voltage bias to reach improved stability of the trapping. Application of a supplemental DC driving field along the trap axis can effectively drive the ion off the trap center and out of the trap, opening up the possibility of studying DNA and other charged molecules using embedded probes while achieving a full control of their translocation and localization in the trap.     

Intracellular recordings of action potentials by an extracellular nanoscale field-effect transistor

The ability to make electrical measurements inside cells has led to many important advances in electrophysiology. The patch clamp technique, in which a glass micropipette filled with electrolyte is inserted into a cell, offers both high signal-to-noise ratio and temporal resolution. Ideally, the micropipette should be as small as possible to increase the spatial resolution and reduce the invasiveness of the measurement, but the overall performance of the technique depends on the impedance of the interface between the micropipette and the cell interior, which limits how small the micropipette can be. Techniques that involve inserting metal or carbon microelectrodes into cells are subject to similar constraints. Field-effect transistors (FETs) can also record electric potentials inside cells, and because their performance does not depend on impedance, they can be made much smaller than micropipettes and microelectrodes. Moreover, FET arrays are better suited for multiplexed measurements. Previously, we have demonstrated FET-based intracellular recording with kinked nanowire structures, but the kink configuration and device design places limits on the probe size and the potential for multiplexing. Here, we report a new approach in which a SiO2 nanotube is synthetically integrated on top of a nanoscale FET. This nanotube penetrates the cell membrane, bringing the cell cytosol into contact with the FET, which is then able to record the intracellular transmembrane potential. Simulations show that the bandwidth of this branched intracellular nanotube FET (BIT-FET) is high enough for it to record fast action potentials even when the nanotube diameter is decreased to 3 nm, a length scale well below that accessible with other methods. Studies of cardiomyocyte cells demonstrate that when phospholipid-modified BIT-FETs are brought close to cells, the nanotubes can spontaneously penetrate the cell membrane to allow the full-amplitude intracellular action potential to be recorded, thus showing that a stable and tight seal forms between the nanotube and cell membrane. We also show that multiple BIT-FETs can record multiplexed intracellular signals from both single cells and networks of cells.     

CMOS compatible nanoscale nonvolatile resistance switching memory

We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.     

Expanding the optical trapping range of lipid vesicles to the nanoscale

Small unilamellar lipid vesicles with diameters down to 50 nm enclosing high refractive index sucrose cores can be optically trapped individually in three dimensions using a focused laser beam. Combined optical trapping and confocal microscopy allows for simultaneous quantitative measurements of the forces exerted on individual vesicles and of their size and shape. The position of individual vesicles in three dimensions is measured with nanometer spatial and ～10 μs temporal resolution.     

Low-cost and nanoscale non-volatile memory concept for future silicon chips

Non-volatile 'flash' memories are key components of integrated circuits because they retain their data when power is interrupted. Despite their great commercial success, the semiconductor industry is searching for alternative non-volatile memories with improved performance and better opportunities for scaling down the size of memory cells. Here we demonstrate the feasibility of a new semiconductor memory concept. The individual memory cell is based on a narrow line of phase-change material. By sending low-power current pulses through the line, the phase-change material can be programmed reversibly between two distinguishable resistive states on a timescale of nanoseconds. Reducing the dimensions of the phase-change line to the nanometre scale improves the performance in terms of speed and power consumption. These advantages are achieved by the use of a doped-SbTe phase-change material. The simplicity of the concept promises that integration into a logic complementary metal oxide semiconductor (CMOS) process flow might be possible with only a few additional lithographic steps.     

Hole trapping in polydiacetylene field effect transistor studied by optical second harmonic generation

Hole trapping in polydiacetylene field effect transistor (PDA-FET) was studied by the electric field induced second harmonic generation (EFISHG). Response of SHG signal from PDA-FET with an application of external voltage was monitored. Applying positive voltage to source and drain electrodes with respect to gate electrode, SHG signal was not observed during bias application, whereas the signal was enhanced after turning off the bias. Since positive bias promotes hole injection from source and drain electrodes, electric field formed by trapped holes in PDA layer activated the SHG signal. Microscopic SHG measurement implies that the trapped holes are concentrated around source and drain electrodes.     

Flexible multi-level quasi-volatile memory based on organic vertical transistor

Driven by important megatrends such as cloud computing,artificial intelligence,and the Internet of Things,as a device used to store programs and data in computing systems,memory is struggling to catch up with the explosive growth of data and bandwidth requirements in the system.However,the storage wair between non-volatile memory and volatile memory retards the further improvement of modern memory computing systems.Herein,a quasi-volatile transistor memory based on organic polymer/perovskite quantum dot blend was fabricated using the vertical transistor configuration.Contributing to vertical structure and appropriate doping ratio of blend film,the quasi-volatile memory device displayed 1,560 times longer data retention time(>100 s)with respect to the dynamic random access memory and fast data programming speed(20 ps)in which was far more quickly than that of other organic non-volatile memories to fill the gap between volatile and non-volatile memories.Moreover,the device retention characteristics could be further promoted under the photoelectric synergistic stimulation,which also provided the possibility to reduce electric writing condition.Furthermore,the quasi-volatile memory device showed good electrical performance under bending conditions.This work provides a simple solution to fabricate multi-level quasi-volatile memory,which opens up a whole new avenue of"universal memory"and lays a solid foundation for low power and flexible random access memory devices.     

A piezoelectric double-mode filter using the complex-branch-type energy trapping

A piezoelectric double-mode filter using the complex-branch-type energy trapping, that is caused by contributions from the complex branches of dispersion curves is proposed, and its theoretical and experimental results are presented for the width-extensional modes in a thin piezoelectric ceramic strip. Characteristics of the symmetric and antisymmetric trapped-energy modes in this filter have some interesting features different from those of the usual trapped-energy modes, such as noticeable undulations in the resonant frequency spectrum and sinusoidally oscillating decay of displacement in the unelectroded region. Based on these results, double-mode filters with a center frequency of about 1 MHz and a 3-dB fractional bandwidth of 3% are constructed. The filters of this type are useful in the medium frequency range below several megahertz because of the miniature size and the ease of supporting.     

Minimum voltage for threshold switching in nanoscale phase-change memory

The size scaling of the threshold voltage required for the amorphous-to-crystalline transition in phase-change memory (PCM) is investigated using planar devices incorporating individual GeTe and Sb2Te3 nanowires. We show that the scaling law governing threshold switching changes from constant field to constant voltage scaling as the amorphous domain length falls below 10 nm. This crossover is a consequence of the energetic requirement for carrier multiplication through inelastic scattering processes and indicates that the size of PCM bits can be miniaturized to the true nanometer scale.     

Threshold voltage shifting for memory and tuning in printed transistor circuits

Multiple mechanisms for controllably shifting the threshold voltage of printed and organic transistors have been identified during the last few years, including some just in the past year, that are analogous in some ways to silicon floating gate memory elements. In addition, printed electronic memory is emerging as a serious product technology for identification and banking cards and for responsive systems through the efforts of startup companies. Other circuit applications are also being identified. Memory and tuning are not as prominently discussed in the literature as simpler and more accessible topics such as display driving, charge carrier mobility, voltage reduction, and high-frequency response. This report summarizes the numerous approaches being considered for the definition and control of transistor threshold voltage in alternative electronic technologies, including the theoretical basis for the effects utilized. Higher and more reliable performance parameters and entirely new functionality are among the advantages to be highlighted.     

MOHOS-type memory performance using HfO2 nanoparticles as charge trapping layer and low temperature annealing

In this work, HfO₂ nanoparticles (np-HfO₂) are embedded within a spin-on glass (SOG)-based oxide matrix and used as a charge trapping layer in metal–oxide–high-k–oxide–silicon (MOHOS)-type memory applications. This charge trapping layer is obtained by a simple sol–gel spin coating method after using different concentrations of np-HfO₂ and low temperature annealing (down to 425 °C) in order to obtain charge–retention characteristics with a lower thermal budget. The memory's charge trapping characteristics are quantized by measuring both the flat-band voltage shift of MOHOS capacitors (writing/erasing operations) and their programming retention times after charge injection while correlating all these data to np-HfO₂ concentration and annealing temperature. Since a large memory window has been obtained for our MOHOS memory, the relatively easy injection/annihilation (writing/erasing) of charge injected through the substrate opens the possibility to use this material as an effective charge trapping layer. It is shown that by using lower annealing temperatures for the charge trapping layer, higher densities of injected charge are obtained along with enhanced retention times. In conclusion, by using np-HfO₂ as charge trapping layer in memory devices, moderate programming and retention characteristics have been obtained by this simple and yet low-cost spin-coating method.     

A single-atom transistor

The ability to control matter at the atomic scale and build devices with atomic precision is central to nanotechnology. The scanning tunnelling microscope can manipulate individual atoms and molecules on surfaces, but the manipulation of silicon to make atomic-scale logic circuits has been hampered by the covalent nature of its bonds. Resist-based strategies have allowed the formation of atomic-scale structures on silicon surfaces, but the fabrication of working devices-such as transistors with extremely short gate lengths, spin-based quantum computers and solitary dopant optoelectronic devices-requires the ability to position individual atoms in a silicon crystal with atomic precision. Here, we use a combination of scanning tunnelling microscopy and hydrogen-resist lithography to demonstrate a single-atom transistor in which an individual phosphorus dopant atom has been deterministically placed within an epitaxial silicon device architecture with a spatial accuracy of one lattice site. The transistor operates at liquid helium temperatures, and millikelvin electron transport measurements confirm the presence of discrete quantum levels in the energy spectrum of the phosphorus atom. We find a charging energy that is close to the bulk value, previously only observed by optical spectroscopy.     

Device modeling of ferroelectric memory field-effect transistor for the application of ferroelectric random access memory

An improved theoretical analysis on the electrical characteristics of ferroelectric memory field-effect transistor (FeMFET) is given. First, we propose a new analytical expression for the polarization versus electric field (P-E) for the ferroelectric material. It is determined by one parameter and explicitly includes both the saturated and nonsaturated hysteresis loops. Using this expression, we then examine the operational properties for two practical devices such as the metal-ferroelectric-insulator-semiconductor field-effect transistor (MFIS-FET) and metal-ferroelectric-metal-insulator-semiconductor field-effect transistor (MFMIS-FET) as well. A double integral also has been used, in order to include the possible effects due to the nonuniform field and charge distribution along the channel of the device, to calculate the drain current of FeMFET. By using the relevant material parameters close to the (Bi, La)/sub 4/Ti/sub 3/O/sub 12/ (BIT) system, accurate analyses on the capacitors and FeMFET's at various applied biases are made. We also address the issues of depolarization field and retention time about such a device.     

Electronic properties of molecular memory circuits on a nanoscale scaffold

Significant challenges exist in assembling and interconnecting the building blocks of a nanoscale device and being able to electronically address or measure responses at the molecular level. Here we demonstrate the usefulness of engineered proteins as scaffolds for bottom-up self-assembly for building nanoscale devices out of multiple components. Using genetically engineered cowpea mosaic virus, modified to express cysteine residues on the capsid exterior, gold nanoparticles were attached to the viral scaffold in a specific predetermined pattern to produce specific interparticle distances. The nanoparticles were then interconnected using thiol-terminated conjugated organic molecules, resulting in a three-dimensional network. Network properties were engineered by using molecular components with different I-V characteristics. Networks consisting of molecular wires alone were compared with networks containing voltage controlled molecular switches with two stable conductance states. Using such bistable molecules enabled the formation of switchable molecular networks that could be used in nanoscale memory circuits.     

Organic nonvolatile memory devices with charge trapping multilayer graphene film

We fabricated an array-type organic nonvolatile memory device with multilayer graphene (MLG) film embedded in polyimide (PI) layers. The memory devices showed a high ON/OFF ratio (over 10(6)) and a long retention time (over 10(4)?s). The switching of the Al/PI/MLG/PI/Al memory devices was due to the presence of the MLG film inserted into the PI layers. The double-log current-voltage characteristics could be explained by the space-charge-limited current conduction based on a charge-trap model. A conductive atomic force microscopy found that the conduction paths in the low-resistance ON state were distributed in a highly localized area, which was associated with a carbon-rich filamentary switching mechanism.     

Capacitorless single transistor dynamic random-access memory devices fabricated on silicon-germanium-on-insulator substrates

Capacitorless single transistor dynamic random-access memory (1T-DRAM) cells on silicon-germanium-on-insulator (SGOI) substrates with various Ge mole fractions in the relaxed-SiGe layers were investigated. SGOI substrates with strained-Si channels showed higher on-currents and carrier mobility than a silicon-on-insulator (SOI) substrate with unstrained-Si channels. SGOI 1T-DRAM devices had larger memory windows than a similar device with SOI; memory window increased with increasing Ge mole fraction in the relaxed-SiGe layer. The SGOI 1T-DRAMs showed degraded retention times. High-temperature annealing reduced the effects of crystalline defects and thus improved the electrical properties of the SGOI substrates, leading to higher carrier mobility, larger memory window, and longer data retention.