Power optimization of multi-level logic circuits utilizing circuit symmetries

The property of circuit symmetry has long been applied to the problem of minimizing the area and timing of multi-level logic circuits. In this paper, we focus on another important design objective, power optimization, utilizing circuit symmetries. First, we analyse and establish the relationship between several types of circuit symmetry and their applicability to reducing power consumption of the circuit, proposing a set of re-synthesis techniques utilizing the symmetries. We derive an algorithm for detecting the symmetries (among the internal signals as well as the primary inputs) on a given circuit implementation. We then propose an effective transformation algorithm to minimize power consumption using the symmetry information detected from the circuit. Unlike many other approaches, our transformation algorithm guarantees monotonic improvement in terms of switching activities, which is practically useful in that user can check the intermediate re-synthesized designs in terms of the degree of changes of power, area, timing, and the circuit structure. We have carried out experiments on MCNC benchmark circuits to demonstrate the effectiveness of our algorithm. On average we reduced the power consumption of circuits by 12% with relatively little increase of area and timing.     

Monte Carlo optimization of superconducting complementary outputswitching logic circuits

The authors have previously proposed a new superconducting voltage-state logic family called complementary output switching logic (COSL). This logic family has been designed using a Monte Carlo optimization process such that circuits have a high theoretical yield at 5-10 Gb/s clock speeds in spite of existing Josephson process variations. In the present work the Monte Carlo optimization process is described and theoretical yields are calculated for the COSL 2- and 3-bit encoder circuits. The circuit simulations use 5-10-GHz sinusoidal clocks and measured global and local process variations. The 2-bit encoder results are compared to modified variable threshold logic (MVTL) circuits and demonstrate that COSL circuits should have a significantly higher theoretical yield than MVTL at 10 Gb/s. Design rules for optimal COSL circuit layouts are also given, and experimental data are presented for 2-bit encoder circuits operating at multigigahertz clock frequencies. HSPICE is used for all Monte Carlo simulations and the Josephson junction model is given in the Appendix     

基于动态逻辑的MPRM电路低功耗优化设计

n个输入变量的逻辑函数有3n种不同的MPRM(Mixed-Polarity Reed-Muller)表达式,其对应电路的功耗和面积不尽相同。本文通过对CMOS电路功耗和动态逻辑MPRM电路低功耗分解方法的分析,建立MPRM电路功耗和面积估计模型,而后提出一种基于动态逻辑的MPRM电路快速低功耗分解算法。在此基础上,针对中小规模和大规模MPRM电路,结合列表转换技术,分别将穷尽搜索算法和遗传算法应用于基于动态逻辑的MPRM电路低功耗优化设计中。通过对MCNC和ISCAS基准电路测试表明:与Boolean电路和FPRM(Fixed-Polarity Reed-Muller)电路相比,中小规模MPRM电路的功耗平均节省80.65%和50.98%,大规模MRPM电路的功耗平均节省69.17%和46.61%。     

Design and investigation of gate-to-gate passive interconnections for SFQ logic circuits

We have developed a method of designing single-flux-quantum (SFQ) logic circuits with passive gate-to-gate interconnections. Based on our method, we designed a 2/spl times/2 switch in which all the interconnections are implemented with passive transmission lines (PTLs) while short Josephson transmission line (JTL) segments are used only to adjust the signal timings. Compared with an identical switch using JTL interconnections, the switch using PTL interconnections has 45% fewer wiring junctions and requires 48% less wiring power current. The switch operated at 40 GHz with a bias margin of /spl plusmn/9.5%.     

Feedthrough in emitter-coupled logic circuits

Emitter coupled logic circuits transient noise behavior is examined. The mechanisms and causes of feedthrough are analyzed using, first, approximate expressions and, second, an accurate model. The experimental observations of feedthrough give ample evidence of good agreement between the theoretical and computational results. An accurate appraisal of the causes of feedthrough, such as C/SUB b//SUB e/, C/SUB b//SUB c/, c/SUB i//SUB d/, C/SUB i//SUB t/, C/SUB p/, and C/SUB c//SUB u//SUB s/ determine the main factors that offer scope for improvement.     

Reliability evaluation of logic circuits

An important guide in the project of logic circuits is the ability to estimate rightly its reliability. In this paper a new type of analysis is presented, by following the references [1], [2], [3] and the method implemented by [4]. This is applicable to all logic circuits, combinational or sequential and by this new structure a reliability matrix is obtained.     

Design and optimization of dual-threshold circuits for low-voltagelow-power applications

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively     

Characterization of integrated logic circuits

The characterization of integrated logic circuits must be accomplished in a manner which fully accounts for the circuit's nonlinear behavior and is amenable to experimental verification. The approach taken in this paper is to describe both the dc and the transient performance of the circuit by developing nonlinear equivalents of the 2-port "black box" parameters used in specifying linear networks. Such terminal parameter characterization has the obvious advantage of eliminating the need to probe the integrated circuit for testing purposes. In addition, knowledge of terminal performance is a necessity when the circuit is studied from a system point of view. In this paper an emitter-coupled logic circuit is used as an example to illustrate the analysis techniques. After accomplishing the terminal parameter characterization of this circuit, attention is directed towards using these results to establish a design procedure. To this end the relationship that exists between power consumption and the circuit safety margins is explored, and the minimum power-delay time product is derived. The analysis accounts for the parasitics which are present in a monolithic integrated circuit and illustrates the use of the nonlinear transistor model.     

Comparison of MOSFET logic circuits

Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.     

Switching nets and electronic logic circuits

It is suggested that methods of improving the reliability of switching nets are not necessarily applicable to electronic logic circuits.     

Cumulative balance testing of logic circuits

We present a new test response compression method called cumulative balance testing (CBT) that extends both balance testing and accumulator compression testing. CBT uses an accumulated balance signature, and it guarantees very high error coverage (over 99%) for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS 85 combinational benchmark circuits is 100%, and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation, provably high error coverage, and exceptionally high SSL fault coverage, even with reduced (nonexhaustive) test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence     

Design methodology for the optimization of transformer-loaded RF circuits

In this paper, a design methodology for the optimization of transformer-loaded RF circuits is presented. The optimization procedure is based on a novel figure of merit for the integrated transformer (namely the transformer characteristic resistance), which was introduced to quantify its performance when operated as a tuned load. Using the proposed approach, a highly linear up-converter for 5-GHz wireless LAN applications was implemented in a 45-GHz-f/sub T/ SiGe HBT technology. The circuit achieved an output 1-dB compression point of 4.5 dBm and a power gain of 18 dB, while drawing only 34 mA from a 3-V power supply.     

Proposal of dual-powered superconducting logic circuits

A novel structure of high-speed Josephson logic circuits is proposed. Josephson logic gates have latching characteristics and can hold data as long as bias currents are supplied. Through effective use of these latching characteristics, logic circuits can be constructed with wide operating margins. Dual power supplies, properly phased, separately drive logic circuits divided into two groups. Logic signals are transferred from one logic group to the other or vice versa, and one group is reset into a zero voltage state when the other group is active for logic operation. For combinational circuits, the basic configuration of an astable flip-flop and a delay circuit are presented to prevent the logic circuit from `racing'. As an example of sequential circuits, a bistable flip-flop to store data is constructed without any superconducting loop.     

`Bootstrapping? in Josephson tunnelling logic circuits

`Bootstrapping? in Josephson tunnelling logic circuits has been realised by providing series connection of multiple junctions and feedback of output current as an additional control current. Computer simulations have demonstrated that the speed-up of the circuits is successfully achieved. This configuration is effective for high-fanout logic circuits, memory peripheral circuits, etc.     

Design and performance evaluation of management service logic execution environment in NGN

This paper introduces a mechanism to solve the service management quick provision problem in next generation network (NGN). The service management logic execution environment (MSLEE) is presented first. The MSLEE is independent of service management contents and network details. The structure of MSLEE with layered universal service management components is also proposed. Then the service management process with double logics is described to illuminate how MSLEE works. At last, MSLEE is modeled using Stochastic Petri net (SPN), and the performance of MSLEE is analyzed based on the simulation experiment with the help of SPNP simulation tool. The experiment result proved that MSLEE is feasible.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.     

Static and dynamic noise margins of logic circuits

Explaining four basic types of noise, and by showing the various methods, together with boundary conditions, which can be used to find the worst case noise margins. A flip-flop setup is advised which can be used for measurements and computer simulations, both for static and dynamic noise margins. Also configurations with fan-in and fan-out larger than 1 can be handled with this flip-flop method. In general, it is found that the dynamic noise margins increase for shorter noise pulses; a first-order explanation of this phenomenon is given. Also, energy noise margins are considered. The theoretical considerations are completed with computer simulations and measurements of the static and dynamic noise margins of integrated Schottky logic (ISL), as an example.     

Low-power tri-state buffer in MOS current mode logic

In this paper, a low-power tri-state buffer in MOS current mode logic (MCML) is proposed. It offers power saving by reducing the overall current flow in the circuit during the high-impedance state. The proposed MCML tri-state buffer is simulated in PSPICE using 0.18 μm TSMC CMOS technology parameters. Its performance comparison with the existing MCML tri-state buffers indicates that the proposed tri-state buffer is power efficient than the others.     

Low-temperature operation of Ge picosecond logic circuits

Low temperature operation of emitter-coupled logic circuits offers potential advantages in reliability, noise immunity, power dissipation, and speed. Experimental picosecond germanium integrated circuits exhibit significant improvements in delay with moderate cooling, in contrast to observed degradation in the performance of comparable silicon circuits. The results of a study of the design factors and performance of germanium circuits at low temperatures are described, with comparisons to silicon. The effect of temperature on circuit propagation delay is emphasized. Brief discussions are included relating observed circuit and transistor temperature dependences to those of more fundamental parameters and processes.