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针对BTID典型信号特点,在传统中频接收机的基础上提出了一种基于FPGA的数字化中频接收机设计方法.介绍了数字接收机的工作原理,分析研究了数字正交解调、数字相关解扩和Viterbi译码算法等关键技术,给出了仿真结果.应用结果表明,接收机满足指标要求,并且结构灵活,抗干扰能力强. 相似文献
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提出了导航接收机中频数字化的一种设计方案,详细分析了该方案中所采用的几种关键技术即带通采样、数字下变频(DDC)、正交解调及高效数字滤波器的设计方法,所给出的软件仿真结果说明该方案的正确性和可行性。 相似文献
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为了解决模拟合成孔径雷达接收机带来的幅相不平衡等诸多问题,设计了一种基于高速A/D转换和FPGA高速信号处理的数字合成孔径雷达中频接收机.该设计结构简单、信号带宽大、镜频抑制比高.对多相滤波正交解调算法进行了改进,给出了数字中频接收机的工作原理和系统结构框图,设计了基于Virtex-4 FPGA的信号处理模块.仿真验证结果表明该设计完全符合系统设计参数的要求,可以应用于高分辨率合成孔径雷达. 相似文献
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本文介绍了数字中频正交解调的基本原理,提出了一种适用于宽带通信系统的数字中频解调实现方案,结合具体实例构建了一个通用硬件平台,并在这个通用硬件平台上通过调用不同的软件实现多种传输速率、多种调制方式的解调功能,该方案可广泛应用于数字化多频段多模式电台(MBMMR)、宽带CDMA、软件无线电等通信系统中。 相似文献
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本文首先介绍了目前较为流行的几种数字接收机结构,分析了中频采样数字接收机关键技术,并给出了基于目前器件技术水平的工程化数字中频接收机实现方案 相似文献
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超宽带正交解调接收机的误差分析与数字补偿方法 总被引:5,自引:0,他引:5
本文提出了超宽带正交解调接收机的误差分析方法,并且针对超宽带线性调频信号,分析了超宽带正交解调误差对脉冲压缩的影响,然后提出了超宽带正交解调误差的数字补偿方法,在实际系统中获得了比较理想的脉冲压缩输出响应。 相似文献
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A receiver concept based on optical quadrature phase-shift keying (QPSK) and a digital realization of synchronous demodulation including phase synchronization is presented. To keep the signal processing bandwidth low a phase diversity receiver, called an intradyne receiver, with an orthogonal electrical demodulation is proposed. Basic principles of the synchronous orthogonal and digital demodulation are described. After the evaluation of the shot noise limit some aspects of the digital phase-locked loop (PLL) are presented. In a 100-Mb/s transmission system a receiver sensitivity of -51.6 dBm has been measured. The loss in relation to the shot noise limit of -66.3 dBm (18 photons/b) is mostly due to the low local laser power and the influence of the receiver input noise 相似文献
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数字正交解调器是软件无线电(SDR)接收机的重要部件,数字混频正交变换法是实现正交解调器的常用算法。本文针对软件无线电中传统数字混频正交变换法算法,根据理论推导,提出一种适用于多频段中频信号的改进结构的数字混频正交变换法。该改进算法将正交解调与低通滤波两个过程结合在一起实现,并且每输入M个输入采样值做一次输出滤波。通过分析和在可编程器件FPGA上的实验表明,该新结构完全实现了数字混频正交变换法,且能较大地减少所占用的FPGA上的RAM和乘法器资源,在相同的FPGA资源条件下,可以较大地提高中频数字正交解调器的邻道隔离性能,或者大幅度提高所允许的前端模数采样器(ADC)的采样频率。 相似文献
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Van Gerwen P. Verhoeckx N. van Essen H. Snijders F. 《Communications, IEEE Transactions on》1977,25(2):238-250
This paper describes the application of a commercially available microprocessor (Intel 3000 or Signetics 3000) to a flexible data transmitter and data receiver for high-speed data modems. For the transmitter a quadrature modulation scheme is chosen; the receiver is based on phase-shift compensation techniques and coherent demodulation with an externally derived digital carrier. For the realization with the given microprocessor it has been necessary to adapt the way of executing the various operations (especially the multiplications for the digital filtering) to the available computational capabilities. The resulting microprocessor implementations are also suitable for application in the current medium-speed synchronous data transmission systems. 相似文献
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A passband digital equalizer is proposed which combines the functions of bandpass filtering and phase splitting with that of adaptive equalization. The new equalizer also provides the in-phase and quadrature outputs required for demodulation. Although input sampling is required at several times the symbol rate (for voice-grade channel applications), outputs need be computed only once per baud. This structure economizes either on front-end analog (phase splitter) filtering or on the number of multiplications required in a digital implementation of a phase splitter and an equalizer. The performance of a receiver incorporating the new equalizer is compared, experimentally, with a receiver using a conventional fractionally spaced (T/2 ) equalizer. 相似文献