Analog circuit diagnosis based on the nullor concept and multiport description of the circuit

The subject of this paper is the fault diagnosis of analog circuits based on the use of nullor concept. The fault location technique presented in the paper can be implemented in the general-purpose analysis program which provides many advantages, of which the most important is the automation of the diagnosis process. A simulation based diagnosis model can be obtained by introducing the norators across the potentially faulty elements and the fixators at the accessible nodes. A practical problem that arises when using this nullor diagnosis model is a lack of an efficient procedure for localization of multiple faults. In the proposed diagnosis technique, the online computational requirements are reduced by introducing a diagnosis model that contains accessible nodes only. The diagnosis model is obtained from the original circuit using relationships among the measured voltages and compensated currents of the faulty elements. The proposed faulty location technique is validated on a benchmark example.     

Fault diagnosis and its prediction in wireless sensor networks using regressional learning to achieve fault tolerance

Due to the wide range of critical applications and resource constraints, sensor node gives unexpected responses, which leads to various kind of faults in sensor node and failure in wireless sensor networks. Many research studies focus only on fault diagnosis, and comparatively limited studies have been conducted on fault diagnosis along with fault tolerance in sensor networks. This paper reports a complete study on both 2 aspects and presents a fault tolerance approach using regressional learning with fault diagnosis in wireless sensor networks. The proposed method diagnose the different types of faulty nodes such as hard permanent, soft permanent, intermittent, and transient faults with better detection accuracy. The proposed method follows a fault tolerance phase where faulty sensor node values would be predicted by using the data sensed by the fault free neighbors. The experimental evaluation of the fault tolerance module shows promising results with R² of more than 0.99. For the periodic fault such as intermittent fault, the proposed method also predict the possible occurrence time and its duration of the faulty node, so that fault tolerance can be achieved at that particular time period for better performance of the network.     

基于神经网络与证据理论的模拟电路故障诊断

论述了利用多类电量测试信息、应用神经网络与D-S证据理论实现模拟电路故障诊断的基本原理,提出了一种基于可测点电压与不同测试频率下的电路增益经决策层信息融合的故障诊断新方法.分别利用此两类测试信息,各用一个独立的改进BP网络对电路进行初步诊断,再运用所提融合诊断算法实现故障定位.模拟实验结果表明:所提方法对硬故障与元件参数偏移较小的软故障均适用,故障定位准确率高.     

基于信息融合技术的模拟电路故障诊断

论述了基于多类电量测试信息模糊融合的模拟电路故障诊断方法的基本原理,提出了分别基于K故障节点诊断法和最小标准差法的元件故障隶属函数构造方法,以及基于可测点电压与不同测试频率下电路增益的模糊信息融合诊断算法.分别利用此两类测试信息及K故障诊断法和最小标准差法,对电路进行初步诊断,再运用模糊变换及故障定位规则,得到融合的故障诊断结果.模拟实验结果表明,所提方法大大提高了故障定位的准确率.     

A New Test Point Selection Method for Analog Continuous Parameter Fault

Discrete hard fault is always tested in existing node selection methods for analog circuit diagnosis. Actually, analog component parameter changes continuously and output node voltages distribute in a continuous voltage interval. In this paper, an novel test node selection method is proposed for continuous parameter shifting (CPS) fault. Firstly, CPS faults are sampled by parameter scan simulation in a single test frequency. Collected node voltages are seen as a data set in a statistical distribution. Secondly, ambiguous faults are identified according to the independent distributions of all CPS faults. The independence of CPS fault sample is deduced by Kruskal-Wallis non-parametric testing. Then, new fault dictionaries are generated for each test node according to ambiguous interval. The proposed fault dictionary represents the mutual independence of each pair of CPS faults. Finally, as fault dictionaries are considered as connected graphs, the optimal test nodes are selected based on an improved depth first search (DFS) algorithm. The effectiveness of method is verified by testing linear and nonlinear circuits.     

Structural Fault Modeling and Fault Detection Through Neyman–Pearson Decision Criteria for Analog Integrated Circuits

A new approach for analog fault modeling and simulation is presented. The proposed approach utilizes the sensitivity of the circuit’s DC node voltages to the process variations and consequently the current deviance so as to differentiate the faulty behavior. A systematic method is proposed for the fault discrimination to minimize the probability that the circuit is accepted as a fault-free when it is faulty. Tests are generated and evaluated taking into account the potential fault masking effects of process spread on the faulty circuit responses. The introduced fault model is validated on a time-interleaved sample-and-hold circuit. Simulation results demonstrate the effectiveness of the model.     

A New Analog Circuit Fault Diagnosis Method Based on Improved Mahalanobis Distance

This paper presents a new analog circuit fault diagnosis method based on improved Mahalanobis Distance. The Mahalanobis Distance is improved according to the characteristics of analog circuit, and then introduced into analog circuit fault detection. First, the circuit testability was analyzed, and the relation of ambiguity groups was determined on the basis of the test matrix, and then the separable potential faulty components under the assumption of single fault were also determined. Finally, the suspicious components could be classified using the improved Mahalanobis Distance according to the feature values of the test points, so as to reduce the number of classes and enhance the speed when classifying faults. The experiment shows that the method can achieve fast analog circuit fault diagnosis and better results of analog circuit diagnosis detection.     

Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors

A neural-network based analog fault diagnostic system is developed for nonlinear circuits. This system uses wavelet and Fourier transforms, normalization and principal component analysis as preprocessors to extract an optimal number of features from the circuit node voltages. These features are then used to train a neural network to diagnose soft and hard faulty components in nonlinear circuits. Our neural network architecture has as many outputs as there are fault classes where these outputs estimate the probabilities that input features belong to different fault classes. Application of this system to two sample circuits using SPICE simulations shows its capability to correctly classify soft and hard faulty components in 95% of the test data. The accuracy of our proposed system on test data to diagnose a circuit as faulty or fault-free, without identifying the fault classes, is 99%. Because of poor diagnostic accuracy of backpropagation neural networks reported in the literature (Yu et al., Electron. Lett., Vol. 30, 1994), it has been suggested that such an architecture is not suitable for analog fault diagnosis (Yang et al., IEEE Trans. on CAD, Vol. 19, 2000). The results of the work presented here clearly do not support this claim and indicate this architecture can provide a robust fault diagnostic system.     

Analog Circuits Fault Detection Using Cross-Entropy Approach

This paper presents a novel method that can detect component faults in analog circuits. Because the probability density function (PDF) of output voltage (current) is sensitive to the components of the circuit, the cross-entropy between the good circuit and the bad circuit is employed to detect component faults in analog circuits based on the autoregressive (AR) model. In the proposed approach, the value of each component of the circuit undertest (CUT) is varied within its tolerance limit using Monte Carlo simulation. The minimal and maximal bounds of the cross-entropy are found for fault-free circuit. While testing, the cross-entropy is obtained. If cross-entropy lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is demonstrated via the second order Sallenkey bandpass filter circuit and continuous-time low pass state-variable filter circuit.     

模拟电路故障诊断的新故障字典法

基于节点电压灵敏度,将文献[1]中的线性无容差电路的故障字典法推广到可以诊断容差模拟电路和非线性电路软故障的新故障字典法。讨论了该方法的原理和字典的建立方法,给出了仿真实例。     

Fault Detection of Analog Circuits Using Network Parameters

A new method to detect component faults in analog circuits is proposed in this paper. Network parameters like driving point impedance, transfer impedance, voltage gain and current gain are used to detect component faults in analog circuits as these network parameters are sensitive to the components of the circuit. Using montecarlo simulation each component of the circuit is varied within its tolerance limit and the minimum and the maximum values of each network parameter are found for fault free circuit. At the time of testing, the network parameters are found for the injected fault and if any one or more network parameters is exceeding its predetermined bound limits then the circuit is confirmed faulty. The proposed method is validated through second order Sallenkey band pass filter and fourth order Chebyshev low pass filter circuits. Numerical results are presented to clarify the proposed method and prove its efficiency.     

Fault-based testing and diagnosis of balanced filters

The test and diagnosis of fully differential analogue filters are addressed in this paper. Full coverage of hard/soft faults affecting circuit behaviour can be achieved by adjusting the tolerance window of the built-in self-test circuitry and the amplitude and frequency of the input test signal. Under a single fault assumption, the faulty active or passive component is located and the actual defective value of a faulty passive component is determined. A test generation procedure which results in maximum fault coverage and maximal diagnosis of hard/soft faults in the filter is presented. The test and diagnosis approach can be made compatible with IEEE Std 1149.1 for boundary scan testing.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

基于闭环集成运放的模拟电路模块级软故障诊断

基于斜率故障模型,提出了一种诊断模拟电路中基于闭环集成运算放大器的模块级软故障的字典法.在由闭环运放组成的模拟电路中,通过对电路以闭环运放及与其输入直接相连的元件看作一个整体划分模块,对各个模块中的任一元件或进行宏模型替代之后的运放等效电路,利用电路中的两节点电压增量计算出的斜率作为统一故障特征,建立故障字典,实现电路中相应模块包含的运放和所有元件的软故障诊断.给出了运放的等效宏模型和模块级软故障的诊断步骤,并用仿真实例证明了该诊断方法的有效性.     

基于虚拟可及测试节点的模拟电路故障诊断

针对网络撕裂方法诊断模拟电路故障过程中撕裂节点必须是可及节点的限制,提出了虚拟可及测试节点的方法.利用网络拓扑结构和基尔霍夫电流定律计算一类不可及测试节点故障电压,让其成为虚拟可及测试节点.然后在可及或虚拟可及测试节点对网络进行撕裂,再根据故障电压和故障判据定位故障至更小的区域,从而进一步定位故障元件.这种新方法降低了待诊断电路中对可及节点数目的要求,增加了撕裂的灵活性.通过仿真实例验证了该方法的有效性.     

Performance analysis and fault tolerance of randomized routing on Clos networks

Beside universality and very low latency, Youssef's randomized self-routing algorithms [25] have high tolerance for multiple faults and more strikingly have the potential for fault tolerance without diagnosis. In this paper we study the performance of Youssef's routing algorithms for faulty Clos networks in the presence of multiple faults in multiple columns with and without fault detection. We show that with fault detection and diagnosis, randomized routing algorithms provide scalable, very efficient and fault tolerant routing mechanisms. Without fault detection and diagnosis, randomized routing provides good fault tolerance for faulty switches in either the first or the second column. The delays become large for faults in the third column or for faults in more than one column. In conclusion, randomized routing enables the system to run without periodic fault detection/diagnosis, and if and when the performance degrades beyond a certain threshold, diagnosis can be performed to improve the routing performance. This revised version was published online in June 2006 with corrections to the Cover Date.     

基于DSP的模拟电路诊断系统的实现

以现代测试技术、信号处理、信息融合等理论为基础,以神经网络在模拟电路故障诊断中的应用为主线,深入研究了模拟电路的故障特征提取和故障诊断方法。用TMS320F2812对选定的待测电路在元件存在容差的条件下,实现了模拟电路软故障诊断。验证了使用DSP实现模拟电路故障诊断系统的可行性。     

Analog circuit fault diagnosis based on noise measurement

In this paper, an analog circuit fault diagnosis method using a noise measurement and analysis approach is suggested. Compared to the conventional circuit fault diagnosis methods, this method can discover hidden and early circuit fault caused by the device defects. Since circuit fault diagnosis is more difficult than device-defect detection, in this paper the circuit output noise calculation, the comparison between the normal and failure conditions and the circuit fault diagnosis method have been discussed. Finally, an example of an active filter circuit fault diagnosis has been given by using this method.     

模拟电路的多频灵敏度故障诊断方法

文章在灵敏度故障诊断方法的基础上提出多频灵敏度参数识别故障诊断方法，并给出选择测试频率的一般原则。该方法能够适用于可及测试节点较少的电路。针对模拟电路中一般只存在部分元件故障的情况，进一步提出只识别部分故障元件参数的多频灵敏度故障诊断方法，使该方法能适用于更大规模的电路。电路仿真结果验证了所提方法的有效性。     

Generation and Verification of Tests for Analog Circuits Subject to Process Parameter Deviations

The paper presents a test stimulus generation and fault simulation methodology for the detection of catastrophic faults in analog circuits. The test methodology chosen for evaluation is RMS AC supply current monitoring. Tests are generated and evaluated taking account of the potential fault masking effects of process spread on the faulty circuit responses. A new test effectiveness metric of probability of detection is defined and the application of the technique to an analog multiplier circuit is presented. The fault coverage figures are therefore more meaningful than those obtained with a fixed threshold.     

Online Fault Tolerance for FPGA Logic Blocks

Most adaptive computing systems use reconfigurable hardware in the form of field programmable gate arrays (FPGAs). For these systems to be fielded in harsh environments where high reliability and availability are a must, the applications running on the FPGAs must tolerate hardware faults that may occur during the lifetime of the system. In this paper, we present new fault-tolerant techniques for FPGA logic blocks, developed as part of the roving self-test areas (STARs) approach to online testing, diagnosis, and reconfiguration . Our techniques can handle large numbers of faults (we show tolerance of over 100 logic faults via actual implementation on an FPGA consisting of a 20 times 20 array of logic blocks). A key novel feature is the reuse of defective logic blocks to increase the number of effective spares and extend the mission life. To increase fault tolerance, we not only use nonfaulty parts of defective or partially faulty logic blocks, but we also use faulty parts of defective logic blocks in nonfaulty modes. By using and reusing faulty resources, our multilevel approach extends the number of tolerable faults beyond the number of currently available spare logic resources. Unlike many column, row, or tile-based methods, our multilevel approach can tolerate not only faults that are evenly distributed over the logic area, but also clusters of faults in the same local area. Furthermore, system operation is not interrupted for fault diagnosis or for computing fault-bypassing configurations. Our fault tolerance techniques have been implemented using ORCA 2C series FPGAs which feature incremental dynamic runtime reconfiguration