用于10 Mb/s和100 Mb/s以太网的时钟数据恢复电路

设计了一个用于10Mb／s和100Mb／s以太同的时钟数据恢复电路，采用双环路结构，增加了系统的稳定性。电路各组成部分的设计进一步增强了锁相环工作的稳定性。电路行为级仿真采用Mentor的ADMS，电路级设计采用Chartered 0．25um CMOS工艺。     

Integrated 100-Gb/s ETDM Receiver

Ethernet in backbone networks has the potential to provide high-performance and cost-efficient networking solutions. Driven by the rapid growth of Ethernet traffic, it is likely that, in the transport network, the next step in terms of the data rate will be 100 Gb/s. In this paper, we report on an integrated electrical-time-division-multiplexing (ETDM) receiver for 100/107 Gb/s, which comprises 1 : 2 demultiplexing and clock-and-data recovery on a single chip. The ETDM receiver was tested successfully in 100- and 107-Gb/s transmission experiments over 480-km dispersion-managed fiber     

一种用于622 Mb/s光纤通讯的时钟恢复电路

提出了一种用于622Mb／s光纤通讯系统的时钟恢复电路。该电路采用改善的正交相关器结构，以改善传统的锁相环捕获范围窄、因环境噪声干扰而失锁的问题。同时，很好地解决了数据恢复电路中时钟和数据的校准问题。压控振荡器(VCO)采用全差分和延时插入技术，以抑制电源和衬底噪声，提高振荡频率范围。该电路采用2μm双板型工艺，在3．3V电压下工作，用Cadence软件进行模拟，捕获时间小于16μs，输出时钟抖动小于0．005UI。     

A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM

A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0/spl deg/, 90/spl deg/, and 270/spl deg/ are generated through the proposed clock adjustment circuits. The latter circuits make input data sampled with an optimized setup/hold window. On-chip input termination with a linearity error of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates. A 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is fabricated in a 0.10-/spl mu/m CMOS process with five metals. The cell size and the chip size are 0.845 /spl mu/m/sup 2/ and 151.1 mm/sup 2/, respectively.     

A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver

This paper describes the design of a 2.5-Gb/s burst-mode optical receiver in a 0.18-mum CMOS process. A dual-gain-mode transimpedance amplifier (TIA) with constant damping factor control is proposed to tolerate a wide dynamic range input signal. By incorporating an automatic threshold tracking circuit (ATC), the TIA and limiting amplifier (LA) are dc coupled with feedforward offset cancellation. Dual-band filters are adopted in the ATC for a rapid response time while keeping the tracking error small. By integrating both a TIA and a post-LA in a single chip, the burst-mode receiver provides a conversion gain of 106 dBmiddotOmega in the high gain mode, 97 dBmiddotOmega in the low gain mode, and a -3-dB bandwidth of 1.85 GHz. The measured input sensitivity, overload level, and dynamic range of the optical receiver are -19 dBm, -2 dBm, and 17 dB, respectively. The response time is less than 50 ns. Operating under a single 1.8-V supply, this chip dissipates only 122 mW.     

Self-Coherent Decision-Feedback-Directed 40-Gb/s DQPSK Receiver

A novel 40-Gb/s differential quadrature phase-shift keying receiver is theoretically proposed, improving direct detection by 4.2 dB for self-phase-modulation-limited single-channel transmission, approaching ideal coherent homodyne performance using a recirculating delay line interferometric integrated-optical circuit front-end combining decision feedback and nonlinear phase-noise compensation     

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-nm CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.      

Real-Time 2.5 GS/s Coherent Optical Receiver for 53.3-Gb/s Sub-Banded OFDM

A real-time receiver for the coherent optical orthogonal frequency-division multiplexing (CO-OFDM) detection is realized in a field-programmable gate array (FPGA). Each building block of the CO-OFDM receiver, such as symbol synchronization, channel estimation, and phase estimation is described and discussed in respect of special technical requirements of real-time implementation. The real-time receiver is successfully demonstrated with a receiver sampling rate of 2.5-Gsamples/s to receive a subband of 53.3-Gb/s multiband CO-OFDM signal. The measured bit error rate (BER) is as low as $3.7times 10^{-8}$ which is a record in real-time or offline CO-OFDM demonstration.      

Clock and data recovery IC for 40-Gb/s fiber-optic receiver

The integrated clock and data recovery (CDR) circuit is a key element for broad-band optical communication systems at 40 Gb/s. We report a 40-Gb/s CDR fabricated in indium-phosphide heterojunction bipolar transistor (InP HBT) technology using a robust architecture of a phase-locked loop (PLL) with a digital early-late phase detector. The faster InP HBT technology allows the digital phase detector to operate at the full data rate of 40 Gb/s. This, in turn, reduces the circuit complexity (transistor count) and the voltage-controlled oscillator (VCO) requirements. The IC includes an on-chip LC VCO, on-chip clock dividers to drive an external demultiplexer, and low-frequency PLL control loop and on-chip limiting amplifier buffers for the data and clock I/O. To our knowledge, this is the first demonstration of a mixed-signal IC operating at the clock rate of 40 GHz. We also describe the chip architecture and measurement results.     

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally     

140Mb/s混合集成光接收机

本文报导了140Mb/s混合集成光接收机的研制结果。接收机全部由厚膜电路集成模块组成。其主放带宽为200MHz(3dB),输出电压V_(pp)值为0.8V,接收灵敏度在10~(-9)误码率下为-39dBm。     

A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems

A high-sensitivity capacitive-coupling receiver is presented for wireless wafer probing systems. The receiver with the optimum logic threshold (OLT) achieves the highest sensitivity of 25 mV at the data rate of 2 Gb/s in 0.18-mum CMOS. The OLT receiver increases the communication distance by more than four times while providing tolerance against distance-voltage-area variations.     

A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique

A 20-Gb/s clock and data recovery circuit incorporates injection-locking technique to achieve high-speed operation with low power dissipation. The circuit creates spectral line at the frequency of data rate and injection-locks two cascaded LC oscillators. A frequency-monitoring mechanism is employed to ensure a close matching between the VCO natural frequency and data rate. Fabricated in 90-nm CMOS technology, this circuit achieves a bit error rate of less than 10^-9 in both continuous (PRBS of 2³¹-1) and burst modes while consuming 175 mW from a 1.5-V supply.     

A 25-Gb/s inductorless SiGe BiCMOS receiver for 100-Gb/s optical links

This paper presents the design and measurements of a 25-Gb/s inductorless optical receiver in a 0.25-μm SiGe BiCMOS process for 100-Gb/s (25-Gb/s × 4 lines) Ethernet. As the first stage of the proposed optical receiver, a transimpedance amplifier (TIA) employing a pseudo-differential structure with a feedback resistor incorporates DC offset cancellation (DOC) to enhance the input dynamic range. Cascaded by the improved two-stage limiting amplifiers and a 50-Ω output buffer, the receiver achieves high differential swings. For a bit-error rate (BER) of 10⁻¹² at 25 Gb/s, the measured transimpedance gain, bandwidth, sensitivity, and output swing are 63.17 dBΩ, 20.7 GHz, −10.3 dBm, and 352.7 mV, respectively. The power consumption of the entire receiver is 111.6 mW and the core area of the die is 640 μm × 135 μm.     

A Low-Power 5-Gb/s Current-Mode LVDS Output Driver and Receiver with Active Termination

In this work, a novel circuit topology for a Low-Voltage Differential Signaling (LVDS) output driver with reduced power consumption is proposed. Also, a low-signal current version of the LVDS driver working with lower supply voltage is proposed along with a compatible differential current-mode receiver. Both the drivers and the receiver feature active-terminated ports that eliminate the need for a dedicated passive terminator for matching. An asymmetric impedance network on the output side of the driver selectively eliminates any reflections coming from the channel while providing a high output impedance to the outgoing signal. For a target signal swing at the receiver input, the proposed termination scheme helps to reduce the driver signal current to up to a third of the current required by a conventional LVDS driver using a passive termination at the output. The asymmetric impedance network consists of a scaled-down replica driver that drives a common drain stage acting as the load for the main driver. The proposed driver topology meeting all LVDS specifications has been implemented in 3.3-V thick-gate CMOS technology. Simulation results show an achievable data rate of 5 Gb/s while transmitting over a 7.5-in FR4 PCB backplane trace for a target BER of 10⁻¹⁵, with power consumption equal to 17.8 mW, which is 25% less than a conventional LVDS driver with passive source end termination producing the same voltage swing at the receiver input. The low-current version of the driver has been implemented in 0.18-μm 1.8-V digital CMOS technology and shows similar performance over the same channel with a power consumption of 4.5 mW.     

Equalization and Clock and Data Recovery Techniques for 10-Gb/s CMOS Serial-Link Receivers

Two equalizer filter topologies and a merged equalizer/CDR circuit are described that operate at 10 Gb/s in 0.13-mum CMOS technology. Using techniques such as reverse scaling, passive peaking networks, and dual- and triple-loop adaptation, the prototypes adapt to FR4 trace lengths up to 24 inches. The equalizer/CDR circuit retimes the data with a bit error rate of 10^-13 while consuming 133 mW from a 1.6-V supply.     

光纤通信端机中用的混合集成AGC信号放大模块

本文报导了140Mb/s混合集成光接收机中所使用的AGC信号放大模块研制结果。此模块为二、三、四次群光通信接收机中的功能模块。它包括主放大器输出信号的平均值检波器、控制二极管衰减器的AGC信号放大器、接收机所接收到的光电平的指示器以及PIN-FET前置放大器过载指示器。该模块采用厚膜混合集成方法将电路密封在DHM24型24引线标准膜电路绝缘子壳内。外形尺寸32.9×20.2mm~2。它体积小,可靠性高,与PIN-FET前放。AGC主放大模块连接后,在实用化的586B线路码型四次群光纤通信系统中,在误码率为10~(-9)下,接收灵敏度为-39dBm,并得到较好的眼图。     

140Mb/s光接收混合集成AGC主放大模块

本文介绍了140Mb/s光通信系统接收机中所用的AGC主放大模块。此模块采用厚膜电路混合集成形式,将AGC电路、主放大器制作在29.1×13.9mm~2的陶瓷片上,封装在DHM24绝缘子壳内,带宽为200MHz(3dB),增益为50dB,AGC范围大于25dB。在四次群光纤通信系统试验中,接收机灵敏度为-39dBm(误码率10~(-9)),眼图清晰。     

A 667-Mb/s operating digital DLL architecture for 512-Mb DDR SDRAM

This paper describes an all-digital delay-locked loop (DLL) architecture for over 667 Mb/s operating double-data-rate (DDR) type SDRAMs, which suppresses skews and jitters. Two novel replica adjusting techniques are introduced, in which timing skews caused by the clock input and data output circuits are reduced by a hierarchical phase comparing architecture and a replica check method with slow tester. Further, an improved phase interpolating method suppresses jitters caused by a boundary of the fine and coarse delays. A 512-Mb test device is fabricated using a 0.13-/spl mu/m DRAM process technology, in which skew and jitter suppressed 667-Mb/s (333-MHz) DDR operation has been verified.     

A 1-Gb/s/pin 512-Mb DDRII SDRAM using a digital DLL and a slew-rate-controlled output buffer

A 1-Gb/s/pin 512-Mb DDRII SDRAM has been developed using a digital delay-locked loop (DLL) and a slew-rate-controlled output buffer. The digital DLL has a frequency divider for DLL input, performs at an operating frequency of up to 500 MHz at 1.6 V, and provides internal clocking with 50% duty-cycle correction. The DLL has a current-mirror-type interpolator, which enables a resolution as high as 14 ps, needs no standby current, and can operate at voltages as low as 0.8 V. The slew-rate impedance-controlled output buffer circuit reduces the output skew from 107 to 10 ps. This SDRAM was tested using a 0.13-/spl mu/m 126.5-mm/sup 2/ 512-Mb chip.