Programmable 2D linear filter for video applications

A fully integrated 2-D linear filter including a line buffer for a 7×7 kernel is presented. To run the filter in real time at video clock frequencies, an array of pipelined carry-save adders was used as a very fast arithmetic unit. The filter chip contains 292451 transistors on a silicon area of 135 mm². The maximum clock frequency under worst-case conditions for technology and temperature was simulated to be 20 MHz. The main blocks are designed as independent parameterizable modules. The line buffer and the arithmetic unit are available as macros in a standard cell library for semicustom design. With these macros a semicustom chip for image enhancement in a X-ray system was produced. This chip works with a system frequency of 13 MHz. The line buffer module is used in another full-custom image processing chip-a two-dimensional rank order filter with a kernel size of also 7×7. This chip contains more than 300000 transistors on a silicon area of 103 mm². In this case the module containing the 1-D FIR (finite impulse response) filters is replaced by additional pixel delays and a sorter module. Simulations have shown that the chip could work with clock frequencies up to 20 MHz     

Easy generation of Dolph-Chebyshev excitation coefficients

New algorithms (I)-(VI) which "generate faster and solve at a lower cost" Dolph-Chebyshev array system equations [1] in the matrical forms AI = P for an array of odd antennas and BI⁰= Q, for even elements array with the respective excitation coefficients I = A^-1P and I⁰= B^-1Q are proposed.     

Large bandwidth BiCMOS operational amplifiers for SC videoapplications

A single-ended and a fully differential broadband BiCMOS operational amplifier for switched-capacitor video applications are presented. The amplifiers feature a folded cascode gain stage with a current source as output load. For the single-ended amplifier the current mirroring is accomplished with a modified bipolar Wilson current mirror at the output of the differential pair. Symbolic expressions for the transfer functions for both amplifiers are derived. The amplifiers are integrated in an analog 1 μm BiCMOS process with an active die area of 0.72 mm² and 0.96 mm² for the single-ended and the fully differential amplifier, respectively. For both amplifiers a DC-gain of 68 dB and a unity gain frequency greater than 250 MHz was measured for a power supply voltage of 5 V     

An 8-b, 40 msamples/s switched-current-mode track-and-hold circuiton a BiCMOS sea-of-gates array

A fully differential track-and-hold circuit based on the switched-current processing has been integrated on a fully complementary 1.2 μm-6 GHz BiCMOS sea-of-gates array. It is based on a BiCMOS switched-current memory cell which uses MOS transistors to store the analog information and bipolar transistors to implement the switch. This improves the speed achievable and the distortion compared to a CMOS-only switched-current memory cell. A differential configuration is also presented which made it possible to improve performances such as the hold mode feedthrough (<-67 dB @ 10 MHz) or the pedestal error. The acquisition time for a full scale step is 22 ns, in order to reach the final value within 0.1%. It achieves 8-b precision at a sample-rate of 40 MHz under Nyquist condition, a full scale track-mode bandwidth of 150 MHz and a consumption of 80 mW for a surface of 0.44 mm²     

A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/sADC array in 1.2-μm CMOS

A 10-bit 5-MS/s successive approximation ADC cell and a 70-MS/s parallel ADC array based on this cell, designed and fabricated in a 1.2-μm CMOS process, are presented. The ADC cell was designed to have an input bandwidth of more than 35 MHz and a sampling time of 14 nS at a clock rate of 70 MHz. The parallel ADC array consists of 14 such cells which are timed in one clock cycle skew successively in order to obtain digitized data every clock cycle. A two-step principle based on unsymmetrical dual-capacitor charge-redistribution-coupling has been used. With the help of a reset function, the comparator presents a fast response to the successive comparison. Each successive approximation ADC cell occupies an area of 0.6 mm² and the core of the parallel ADC array occupies an area of 2.7×3.3 mm². The power consumptions for the cell and the parallel ADC array are 18 mW and 267 mW respectively     

A 64-kbit block addressed charge-coupled memory

This paper describes the design and performance of a 64-kbit (65 536 bits) block addressed charge-coupled serial memory. By using the offset-mask charge-coupled device (CCD) electrode structure to obtain a small cell size, and an adaptive system approach to utilize nonzero defect memory chips, the system cost per bit of charge-coupled serial memory can be reduced to provide a solid-state replacement of moving magnetic memories and to bridge the gap between high cost random access memories (RAM's) and slow access magnetic memories. The memory chip is organized as 64K words by 1 bit in 16 blocks of 4 kbits. Each 4-kbit block is organized as a serial-parallel-serial (SPS) array. The chip is fully decoded with write/recirculate control and two-dimensional decoding to permit memory matrix organization with X-Y chip select control. All inputs and the ouput are TTL compatible. Operated at a data rate of 1 MHz, the mean access time is about 2 ms and the average power dissipation is 1 µW/bit. The maximum output data rate is 10 MHz, giving a mean access time of about 200 µs, and an average power dissipation of 10 µW/bit. The memory chip is fabricated using an n-channel polysilicon gate process. Using tolerant design rules (8-µm minimum feature size and ±2-µm alignment tolerance) the CCD cell size is 0.4 mil²and the total chip size is 218 × 235 mil². The chip is mounted in a 22-pin 400-mil wide ceramic dual in-line package.     

BER performance of CMA adaptive array for high-speed GMSK mobilecommunication-a description of measurements in central Tokyo

This paper describes the performance of an adaptive array as a countermeasure to multipath fading for a 256 kbps Gaussian-filtered minimum shift keying (GMSK) mobile communication system operating in the 1.5 GHz band. An adaptive array having four antenna elements is implemented using the digital beam forming concept. The constant modulus algorithm (CMA) is employed for the adaptation process to ease the implementation. Measurements in central Tokyo of the bit error rate (BER) performance and an array pattern arising in the multipath environment are presented. Analysis of the array pattern confirms that the array succeeds in directing nulls to the delayed signals. BER performance shows an improvement in E_b/N₀, compared with that of a single antenna system, of 17.5 to 22 dB at a BER of 1.0×10^-2 in a frequency-selective fading channel     

An array processor for general purpose digital image compression

A new VLSI processor (DIP chip) for image compression is presented which combines principles of multipipeline and array processing. The device is not specific to any one image compression algorithm and can be regarded as a general purpose processor. The chip has been implemented using a CMOS 1.0-μm process on a 14.4×13.5-mm² die. An internal clock frequency of 40 MHz results in 1.2×10⁹ operations/s on 8-bit data. Solutions to problems associated with the large bandwidth required, for both image data and instruction streams, is the main aim of the paper. The necessary problem of increasing the array clock frequency relative to the input/output clock frequency without the need for a large on-chip instruction cache or fast external clock speeds is also addressed     

A one-wire approach for skew-compensating clock distribution basedon bidirectional techniques

A clock-deskew buffer using the delay-locked loop and the bidirectional technique has been developed. It needs only one wire to synchronize the clocks for a chip-to-chip system. It has been fabricated by a 0.35-μm n-well CMOS process. Experimental results demonstrate that it can achieve the peak-to-peak jitter smaller than 100 ps through a two-meter coaxial cable while operating at the frequency of 120 MHz. The total power dissipation of the skew buffer is 218 mW for a 3 V supply. The core chip area is 980×1700 μm²     

Field effect transistor-self electrooptic effect device (FET-SEED)differential transimpedance amplifiers for two-dimensional optical datalinks

A 4×18 two-dimensional array of GaAs FET-SEED (field effect transistor-self electrooptic effect device) differential transimpedence receivers has been fabricated for application in massively parallel optical data link board-to-board interconnections. Several FET-SEED receiver arrays were tested and displayed a mean response of ~0.7 mV/μW, and were capable of >100 Mbps per channel operation. The mean receiver sensitivity for a BER of <10^-9 was calculated from the measured noise spectrum to be -26.8 dBm at the system design rate of 40 Mbps (18 k-22 MHz bandwidth), and -23.2 dBm for a 100 Mbps rate (dc-66 MHz bandwidth). A sensitivity of approximately -25 dBm for the 40 Mbps rate was confirmed using a bit-error-rate test set. The theoretical noise is compared to measured values with good agreement assuming a FET channel noise factor of 1.4. The 1/f noise corner frequency of ~13 MHz was found to cause a ~1.2 dB degradation in sensitivity for the 100 Mbps rate. The differential amplifier mean dc output offset voltage was measured to be 10 mV, and displayed a large sigma due to parameter variations in the active devices. Two receiver arrays were successfully used in a demonstration of a fully differential parallel optical small computer system interface (SCSI) data link     

High-performance phase locking of wide linewidth semiconductorlasers by combined use of optical injection locking and opticalphase-lock loop

The requirement for narrow linewidth lasers or short-loop propagation delay makes the realization of optical phase-lock loops using semiconductor lasers difficult. Although optical injection locking can provide low phase error variance for wide linewidth lasers, the locking range is restricted by stability considerations. Theoretical and experimental results for a system which combines both techniques so as to overcome these limitations, the optical injection phase-lock loop (OIPLL), are reported. Phase error variance values as low as 0.006 rad ² (500 MHz bandwidth) and locking ranges exceeding 26 GHz were achieved in homodyne OIPLL systems using DFB lasers of summed linewidth 36 MHz, loop propagation delay of 15 ns and injection ratio less than -30 dB. Phase error variance values as low as 0.003 rad² in a bandwidth of 100 MHz, a mean time to cycle slip of 3×10¹⁰ s and SSB noise density of -94 dBc/Hz at 10 kHz offset were obtained for the same lasers in an heterodyne OIPLL configuration with loop propagation delay of 20 ns and injection ratio of -30 dB     

An integrated optic RE spectrum analyzer in a ZnO-GaAs-AlGaAswaveguides

A report is presented on the realization of an integrated optic RF spectrum analyzer (IOSA) that combines a wideband acoustooptic Bragg cell and a pair of waveguide lenses in ZnO/GaAs/Al_0.15Ga_0.85As composite waveguide 7×23 mm² in size. A total of 10 and 40 channels at the center frequencies of 167 MHz and 500 MHz, respectively, and a frequency resolution of 5.5 MHz were realized. The diffraction efficiencies of 11.5%/W and 4.0%/W of RF drive power at the center frequencies of 167 MHz and 500 MHz, respectively, and a dynamic range larger than 16 dB were measured. Further integration of this IOSA (integrated optic spectrum analyzer) with a laser source, a photodetector array, and electronic driving circuits could produce a monolithically integrated optic RF spectrum analyzer     

High-sensitivity capacitive sensing interfacing circuit for monolithic CMOS M/NEMS resonators

A simple and high-sensitivity 0.35 mum CMOS readout circuit for resonant M/NEMS with capacitive sensing is presented. The proposed readout scheme presents an equivalent transimpedance gain of 140 dB Omega (at 1 MHz) and an input referred noise of 29 nV/Hz^1/2. Detection of submicrometre-scale cantilever vibrations in the MHz range is demonstrated with a displacement resolution of 33 ffn/Hz^1/2.     

An efficient VLSI architecture for real-time additive synthesis ofmusical signals

This paper presents a new architecture for the hardware implementation of additive synthesis for high-quality musical sound generation. A marginally stable second-order infinite-impulse-response filter is used to generate each sinusoid, the frequency, amplitude, and phase of which can independently be specified. A chip has been designed with a bit-level systolic array approach. It is capable of performing 1200 sinusoid real-time synthesis. Furthermore, it is possible to connect up to 11 chips, to achieve an outstanding 13 200 sinusoid synthesis. Two completely independent output channels are available as 20-b streams. The system is clocked at 60 MHz when working with a 44.1-kHz sampling rate. The integrated circuit is designed in a 0.5-μm CMOS technology and has a core area of approximately 19 mm²     

Influence of laser phase on 400-Mbit/s coherent optical DPSK system

The influence of laser phase noise on a 400-Mb/s optical DPSK (differential phase-shift keying) system is experimentally investigated with linewidths ranging from 1.2 MHz to 8 MHz. This range corresponds to linewidth to bit rate ratios ϵ of 0.33-2%. The system performance with these nonzero linewidths is evaluated against a negligible linewidth performance baseline. The sensitivity degradation at a bit error rate of 10^-9 increases from 1.8 to 7 dB as ϵ is increased from 0.33-1%. When ϵ is increased beyond 1%, bit error rate floors higher than 10^-9 develop. These findings agree well with the existing theories and allow the generalization of these results to other bit rates, as well as establishing practical criteria for lasers to be used in DPSK systems     

酒精蒸汽近红外高分辨光谱获取方法研究

酒精是相对复杂的分子,在常压下为宽带吸收,其OH基团的泛频吸收区位于近红外7000～7300cm-1处.利用可调谐二极管激光光谱学(TDLAS)方法测量了含有少量水汽的酒精蒸汽在7180 cm-1附近的吸收谱线,通过多项式拟合消除水汽吸收谱线干扰,获得了酒精蒸汽的特征吸收光谱,其半高半宽为1.3cm-1;并对不同浓度酒精蒸汽吸收谱线线型做了研究,证明其线型与酒精分压不相关,为发展基于TDLAS酒驾遥测技术奠定了基础.     

An Ultra-Wideband Distributed Active Mixer MMIC in 0.18-μm CMOS Technology

In this paper, a distributed circuit topology for active mixers suitable for ultra-wideband operations is presented. By employing nonuniform artificial transmission lines with the complementary transconductance stages in the Gilbert-cell multiplier, the proposed mixer demonstrates broadband characteristics at microwave frequencies while maintaining a high conversion gain (CG) with improved gain flatness. Using a 0.18-mum CMOS process, the proposed circuit is implemented, exhibiting a -3-dB bandwidth of 28 GHz. With a local-oscillator power of 3 dBm and an IF frequency of 10 MHz, the fabricated circuit has a CG of 12.5plusmn1 dB and an average input third-order intercept point (IIP₃) of 0 dBm within the entire frequency range. The fully integrated wideband mixer occupies a chip area of 0.87times0.82 mm² and consumes a dc power of 20 mW from a 2-V supply voltage     

A study of frequency response in silicon heterojunction bipolartransistors with amorphous silicon emitters

A detailed physical model of amorphous silicon (a-Si:H) is incorporated into a two-dimensional device simulator to examine the frequency response limits of silicon heterojunction bipolar transistors (HBT's) with a-Si:H emitters. The cutoff frequency is severely limited by the transit time in the emitter space charge region, due to the low electron drift mobility in a-Si:H, to 98 MHz which compares poorly with the 37 GHz obtained for a silicon homojunction bipolar transistor with the same device structure. The effects of the amorphous heteroemitter material parameters (doping, electron drift mobility, defect density and interface state density) on frequency response are then examined to find the requirements for an amorphous heteroemitter material such that the HBT has better frequency response than the equivalent homojunction bipolar transistor, We find that an electron drift mobility of at least 100 cm² V^-1 s^-1 is required in the amorphous heteroemitter and at a heteroemitter drift mobility of 350 cm ² V^-1 s^-1 and heteroemitter doping of 5×10¹⁷ cm^-3, a maximum cutoff frequency of 52 GHz can be expected     

Dual-resonant π-shape with double L-strips PIFA for implantable biotelemetry

A compact -shape with a double L-strips planar inverted-F antenna (PIFA) is proposed for implantable biotelemetry in the Medical Implant Communication Services band (MICS band). The antenna occupies a volume of only 643 mm³ (22.5 22.5 1.27 mm), operating frequency at 402 MHz. Utilising the -shape with the double L-strips PIFA structure can excite dual-resonate frequencies that control the dual-resonant frequency at 375 and 427 MHz to obtain the broad bandwidth of 80 MHz (362 442 MHz) at return loss of 10 dB. To demonstrate the performance of the implantable antenna more efficiently, the simulating skin fluids are also developed by varying alcohol concentration with salts. Thus, provided is a miniature, broadband implantable PIFA for biotelemetry with medical devices.     

基于全天空流星雷达测量动量通量的新方法

全天空流星雷达是新一代的流星雷达, 可以接收流星余迹反射的无线电波, 目前主要应用于探测流星烧蚀区域的大气风场进而研究该区域的大气动力学.文中利用全天空流星雷达, 基于Hocking提出的测量重力波动量通量的新方法来研究昆明地区的大气环境参数—重力波的动量通量.由于采样时间间隔的不同, 该方法仍存在争议.本文主要利用昆明站工作频率为37.5 MHz的全天空流星雷达测得的流星数据来验证采样时间对重力波动量通量取值的影响, 同时利用工作频率分别为37.5 MHz、53.1 MHz的全天空流星雷达在2014年9月份观测的数据对该方法进行了对比分析, 结果表明:采样时间间隔的选取对重力波动量通量的取值有很大影响; 在合适的采样时间间隔内利用全天空流星雷达测量重力波的动量通量的新方法是可行的.