Design and performance analysis of InP-based high-speed andhigh-sensitivity optoelectronic integrated receivers

A novel transimpedance optoelectronic receiver amplifier suitable for monolithic integration is proposed and analyzed by exploiting state-of-the-art high-speed MSM photodiodes and HBT's based on lattice-matched InGaAs-InAlAs heterostructures on InP substrates. The projected performance characteristics of this amplifier indicate a high transimpedance (≈3.6 kΩ), a large bandwidth (17 GHz), and an excellent optical detection sensitivity (-26.8 dBm) at 17 Gb/s for the standard bit-error-rate of 10^-9. The latter corresponds to an input noise spectral density, √(i_in²/B), of 2.29 pA/√(Hz) for the full bandwidth. The bandwidth of the amplifier can be increased to 30 GHz for a reduced transimpedance (0.82 kΩ) and a lower detection sensitivity, i.e., -21 dBm at 30 Gb/s. The amplifier also achieves a detected optical-to-electrical power gain of 21.5 dBm into a 50 Ω load termination. The design utilizes small emitter-area HBT's for the input cascoded-pair stage, followed by a two-step emitter-follower involving one small and one large emitter-area HBT's. The design strategy of using small emitter-area HBT's is matched by a low-capacitance novel series/parallel connected MSM photodiode. This combined approach has yielded this amplifier's combined high performance characteristics which exceed either achieved or projected performances of any receiver amplifier reported to-date. The paper also discusses the issues concerning IC implementation of the receiver, including the means of realizing a high-value feedback resistor     

A monolithic field emitter array with a JFET

This paper proposes a novel structure of the conical Si field emitters monolithically incorporating a vertical-type junction field effect transistor (JFET) and demonstrates the emission control in field emission from the emitters. The proposal has many attractive advantages in the display application and reliable fabrication, because the structure needs neither additional area for the JFET nor additional process except ion implantation. The experimental results of the emitters show excellent controllability and stability in the emission current     

Cadmium sulfide surface stabilization for InP-based optoelectronic devices

Thin layers of chemical bath deposited cadmium sulfide were used to improve the surface and interface properties of InP and its latticed-matched III-V compounds. X-ray photoelectron spectroscopy indicates chemical reduction of surface oxides and the prevention of subsequent group III or V oxide formation. Photoluminescence spectra, measured between 1.0 and 1.3 μm, indicate a dramatic reduction in phosphorus vacancies following CdS treatment. Metalinsulator-semiconductor capacitors fabricated onn-type InP substrates with CdS interlayers display near-ideal quasi-static response and interface-state densities in the low 10¹¹/eVcm² range. Thin CdS layers were used to passivate the surface of InAlAs/InGaAs high electron mobility transistors (HEMTs) and metal-semiconductor-metal (MSM)photodetectors.AfterCdS treatment, Schottky diode barrier heights of 0.6 eV were regularly obtained. For HEMTs, drain-togate current ratios of 8 × 10⁴ were observed after CdS treatment. For a new backside illuminated MSM design, the dark current of CdS-treated samples was reduced three orders of magnitude to below 1 nA.     

A monolithic low-power high-voltage driver for bistable LCDs

A complete low-power high-voltage driver for a 80×104 passive-matrix bistable LCD is integrated in a 0.7 μm CMOS smart-power technology. It features 100 V driving capability on all row and column outputs and comprises all necessary digitally programmable high-voltage generators and multiplexers to synthesize the required complex high-voltage waveforms from a 3 V battery. An original level-shifter design for the high-voltage multiplexers and a dedicated architecture for the programmable high-voltage generators yield an extremely low internal power consumption below 10 mW for the entire driver chip.     

A low-power 128-MHz VCO for monolithic PLL ICs

The phase-locked loop (PLL) is implemented by 2-μm bipolar-CMOS (BiCMOS) technology. The power dissipation of the PLL and the voltage-controlled oscillator (VCO) are 100 mW at 64 MHz and 25 mW for 1-128 MHz clock frequencies, respectively. The linearity of the VCO is ±0.5% and the temperature stability is ±50 p.p.m./°C. The center frequency of the VCO is accurately set by using one fixed external resistor. The VCO has an advantage of noise insensitivity. To achieve these features, the VCO design uses an emitter-coupled multivibrator with a built-in timing capacitor and a controlled oscillation loop gain. The PLL can be applied not only to timing recovery for data transmission, but also to frequency synthesis and self-clocking for data recording     

A low-power monolithic CMOS transceiver for 802.11b wireless LANs

A single-chip low-power transceiver IC operating in the 2.4 GHz ISM band is presented. Designed in 0.18 μm CMOS, the transceiver system employs direct-conversion architecture for both the receiver and transmitter to realize a fully integrated wireless LAN product. A sigma-delta (∑△) fractional-N frequency synthesizer provides on-chip quadrature local oscillator frequency. Measurement results show that the receiver achieves a maximum gain of 81 dB and a noise figure of 8.2 dB, the transmitter has maximum output power of-3.4 dBm and RMS EVM of 6.8%. Power dissipation of the transceiver is 74 mW in the receiving mode and 81 mW in the transmitting mode under a supply voltage of 1.8 V, including 30 mW consumed by the frequency synthesizer. The total chip area with pads is 2.7×4.2 mm2.     

Intermixing of InP-based multiple quantum wells for integrated optoelectronic devices

The intermixing characteristics of three widely used combinations of InP-based quantum wells (QW) are investigated using the impurity-free vacancy disordering (IFVD) technique. We demonstrate that the bandgap energy shift is highly dependent on the concentration gradient of the as-grown wells and barriers, as well as the thickness of the well, with thinner wells more susceptible to interdiffusion at the interface between the barrier and well. According to our results, the InGaAsP/InGaAsP and InGaAs/InP are well suited for applications requiring a wide range of bandgap values within the same wafer. In the case of the InGaAs/InGaAsP system, its use is limited due to the significant broadening of the photoluminescence spectrum that was observed. The effect of the top InGaAs layer over the InP cladding is also investigated, which leads to a simple way to obtain three different bandgaps in a single intermixing step.     

A new successive approximation architecture for high-speed low-power ADCs

A new high-speed successive approximation analog-to-digital converter (ADC) architecture is presented. Two-bits extraction in each clock cycle is the key idea to double the conversion speed. Generating reference levels for three comparators with only two digital-to-analog converter (DACs), is another novelty of the new architecture. The proposed DAC structure allows a substantial reduction in overall control logic complexity. A 10-bit 40 Ms/S successive approximation ADC was designed based on the proposed architecture in CMOS technology. The simulation results show that the proposed architecture introduces 7% reduction in power consumption over conventional architecture. Furthermore, chip area for the new ADC is 40% less than what otherwise would be needed by an ADC using conventional architecture.     

A monolithic high-speed sample-and-hold amplifier for digital audio

A monolithic high-speed sample-and-hold amplifier is described which has an acquisition time of 1.5 /spl mu/s to 0.001% for a 10-V step and an aperture uncertainty of less than 0.5 ns. Distortion is 0.001% over the audio band, while in an A/D and D/A converter loop a signal-to-noise ratio better than 90 dB is measured. Chip size is 1.5/spl times/2.5 mm/SUP 2/.     

A high-speed low-power rail-to-rail column driver for AMLCD application

A high-speed rail-to-rail low-power column driver for active matrix liquid crystal display application is proposed. An inversion controller is attached to a typical column driver for rail-to-rail operation. Two high-speed complementary differential buffer amplifiers are proposed to drive a pair of column lines and to realize a rail-to-rail and high-speed drive. The output buffer amplifier achieves a large driving capability by employing a simple comparator to sense the transients of the input to turn on an auxiliary driving transistor, which is statically off in the stable state. This increases the speed without increasing static power consumption. The experimental prototype 6-bit column driver implemented in a 0.35-/spl mu/m CMOS technology demonstrates that the driver exhibits the maximum settling times of 1.2 /spl mu/s and 1.4 /spl mu/s for rising and falling edges with a dot inversion under a 680-pF capacitance load. The static current consumptions are 4.7 and 4.2 /spl mu/A for pMOS input buffers and nMOS input buffers, respectively. The values of the differential nonlinearity (DNL) and integral nonlinearity (INL) are less than 1/2 LSB.     

A high-speed, low-power clock generator for a microprocessorapplication

This paper discusses the design of the clock generator for the Alpha 21264. As the speed performances are of primary concern in the whole design, the clock-generator jitter and phase misalignment must be as low as possible in a very noisy environment. A dedicated on-chip voltage regulator based on a bandgap reference has been designed to reduce the effect of supply noise on the clock generator. To avoid a large voltage drop across the power-supply bond wires during the startup sequence, the core frequency can be increased by steps in one period of the core clock, with a limited frequency overshoot and no missing pulses. The circuit has been implemented in a CMOS 0.35 μm process. The voltage-controlled-oscillator frequency range is between 350 MHz and 2.8 GHz, with a peak-to-peak cycle-to-cycle jitter lower than 16 ps. While booting Unix on a system, the maximum phase misalignment is lower than ±100 ps     

一种低功耗高速空间光调制器驱动电路

本文描述了一种新型的多量子阱空间光调制器驱动电路的设计和测试。为了解决时钟同步问题并减少功耗,我们有别于前人,将所有电路模块集成在一块芯片上。因为传统的单斜坡数模转换器无法消除电容的失配,所以我们转而采用64个列共享8位电阻串数模转换器来提供输出电压,实现0.5V至3.8V的可编程电压调控。这些数模转换器被紧密放置于6464 驱动阵列的上方力求减小失配。每个转换器消耗80uA电流,在280ns内完成一次转换。为了更快的传输速率,系统采用2级缓存,工作时钟50MHz,真刷新率达到50K帧每秒,整片功耗302mW。芯片采用0.35um CMOS工艺,面积5.5 mm7 mm。     

AlGaAs/GaAs HBT IC's for high-speed lightwave transmission systems

The implementation of multigigabit-per-second optical communication systems requires many high-speed electronic circuit components that meet stringent performance requirements. Several important research prototype circuits for fiber-optic transmission, implemented in a baseline AlGaAs/GaAs HBT process, are discussed. These include a 20 Gb/s decision circuit, a 27 Gb/s 1:2 demultiplexer, a 30 GB/s 2:1 multiplexer, a 27 Gb/s 4:1 multiplexer, and a 11 Gb/s laser driver IC     

A design for high-speed low-power CMOS fully parallelcontent-addressable memory macros

Described is a design for high-speed low-power-consumption fully parallel content-addressable memory (CAM) macros for CMOS ASIC applications. The design supports configurations ranging from 64 words by 8 bits to 2048 words by 64 bits and achieves around 7.5-ns search access times in CAM macros on a 0.35-μm 3.3-V standard CMOS ASIC technology. A new CAM cell with a pMOS match-line driver reduces search rush current and power consumption, allowing a NOR-type match-line structure suitable for high-speed search operations. It is also shown that the CAM cell has other advantages that lead to a simple high-speed current-saving architecture. A small signal on the match line is detected by a single-ended sense amplifier which has both high-speed and low-power characteristics and a latch function. The same type of sense amplifier is used for a fast read operation, realizing 5-ns access time under typical conditions. For further current savings in search operations, the precharging of the match line is controlled based on the valid bit status. Also, a dual bit switch with optimized size and control reduces the current. CAM macros of 256×54 configuration on test chips showed 7.3-ns search access time with a power-performance metric of 131 fJ/bit/search under typical conditions     

A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters

This paper presents a partially switched-opamp technique for a high-speed, low-power pipelined analog-to-digital converter (ADC). Unlike a conventional switched-opamp technique, only the second stage of a two-stage opamp is switched with the enhanced power efficiency and the drawbacks of an opamp sharing technique and a conventional switched-opamp technique are addressed. The prototype of 8-bit 200-MS/s pipelined ADC is implemented in a 0.18-/spl mu/m CMOS process technology. This converter achieves 55.8-dB spurious free dynamic range, 47.3-dB signal-to-noise-plus-distortion ratio, 7.68 effective number of bits for a 90-MHz input at full sampling rate, and consumes 30-mW from a 1.8-V supply. The active area of the ADC is 0.15 mm/sup 2/.     

一种高速低功耗BiCMOS脉冲式触发器的通用结构

BiCMOS电路兼具CMOS电路高集成度,低功耗的优点和双极型电路高速大驱动能力的优势,已成为目前国际学术界研究的热点之一。本文提出了一种基于BiCMOS工艺的新型脉冲式触发器的通用结构和设计方法,并设计了两种结构简单的BiCMOS脉冲式D型触发器。应用TSMC 180nm工艺,采用HSPICE模拟表明:所设计的BiCMOS脉冲式D型触发器不仅具有正确的逻辑功能,而且具有高速低功耗大驱动能力的优点,与已有文献提出的BiCMOS D型触发器相比,功耗和PDP均有大幅度降低。     

A high-speed four-phase clock generator for low-power on-chip SerDes applications

In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for on-chip SerDes applications. The device utilizes a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics 65 nm process technology using only 125 transistors and it occupies an active area of under 2.34 μm². With a power supply of 1.1 V the complete circuit consumes 89.56 μW at room temperature.     

A low-power,fast-settling reference circuit for high-speed high-resolution ADC

A low-power, fast-settling reference buffer used for high-speed high-resolution ADC is proposed. A replica buffer forms a closed loop to stabilise the operating point and a cascaded gm-boosting technique provides sufficient low output impedance, all of which ensure a high performance for the proposed buffer. The measured results show that the proportion of power consumption by the proposed buffer over ADC is only 2.7%, while settling to 12-bit accuracy within 0.13 ns.     

VLSI circuits for low-power high-speed asynchronous addition

This paper presents a new low-power high-speed fully static CMOS variable-time adder. The VLSI implementation proposed here is based on the statistical carry look-ahead addition technique. The new circuit takes advantage of an innovative way of using a composition of propagate signals and of appropriately designed overlapped execution modules to reduce average addition time, layout area, and power dissipation. A 56-bit adder designed as described here and realized using AMS 0.35-/spl mu/m CMOS standard cells at 3.3V supply voltage shows an average addition time of about 4.3 ns and a maximum power dissipation of only 50 mW at 200-MHz repetitive frequency using a silicon area of less than 0.23 mm/sup 2/.     

BiCMOS nonthreshold logic for high-speed low-power applications

New high-speed low-power BiCMOS nonthreshold logic (BNTL) circuits are presented. These circuits offers a built-in CMOS and bipolar level conversion and are suitable for reduced power supply voltage. A 4-b carry lookahead generator (CLG) circuit is designed in BNTL, ECL, and CMOS using 0.8-μm BiCMOS technology. Circuit simulations show that this new logic provides speed comparable to or better than that provided by emitter-coupled logic (ECL) for lower power dissipation