Distributed architectures and logical-task decomposition inmultimedia surveillance systems

In the past few years, the development of complex surveillance systems has captured the interest of both the research and industrial worlds. Strong and challenging requirements of modern society are involved in this problem, which aims to increase safety and security in several application domains such as transport, tourism, home and bank security, military applications, etc. At the same time, fast improvements in microelectronics, telecommunications, and computer science make it necessary to consider new perspectives in this field. The main objective of this paper is to investigate, discuss, and evaluate the impact of distributed processing and new communication techniques on multimedia surveillance systems, which represent the so-called third-generation surveillance systems (3 GSSs). In particular, aspects related to the distribution of intelligence among multiple-processing and wide-bandwidth resources are discussed in detail. It is shown how distribution of intelligence can be obtained by a hierarchical architecture that partitions, in a dynamic way, the main logical processing tasks (i.e., representation, recognition, and communication) performed in a 3 GSS physical architecture made up of intelligent cameras, hubs, and central control rooms. The advantages of this solution are pointed out in terms of 1) increased flexibility and reconfigurability and 2) optimal allocation of available processing and bandwidth resources. Finally, a case study is analyzed that allows one to gain a deeper insight into a distributed surveillance system     

Array architectures for iterative algorithms

Regular mesh-connected arrays are shown to be isomorphic to a class of so-called regular iterative algorithms. For a wide variety of problems it is shown how to obtain appropriate iterative algorithms and then how to translate these algorithms into arrays in a systematic fashion. Several "systolic" arrays presented in the literature are shown to be specific cases of the variety of architectures that can be derived by the techniques presented here. These include arrays for Fourier Transform, Matrix Multiplication, and Sorting.     

Communication architectures for electrical drives

The paper gives an overview of the communication architectures adopted in the industrial automation for the electrical drives, ensuring a fast data exchange and high performance control. An attempt is made at defining real-time operation for this application field, at reviewing the standardization work done to unify the electrical drive interfaces, and at encompassing the recently accepted solutions, including those based on the industrial Ethernet.     

VLSI array algorithms and architectures for RSA modularmultiplication

We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are designed for Rivest-Shamir-Adelman (RSA) cryptography and are based on the familiar iterative Horner's rule, but use precalculated complements of the modulus. The problem of deciding which multiples of the modulus to subtract in intermediate iteration stages has been simplified using simple look-up of precalculated complement numbers, thus allowing a finer-grain pipeline. Both algorithms use a carry save adder scheme with module reduction performed on each intermediate partial product which results in an output in carry-save format. Regularity and local connections make both algorithms suitable for high-performance array implementation in FPGA's or deep submicron VLSI. The processing nodes consist of just one or two full adders and a simple multiplexor. The stored complement numbers need to be precalculated only when the modulus is changed, thus not affecting the performance of the main computation. In both cases, there exists a bit-level systolic schedule, which means the array can be fully pipelined for high performance and can also easily be mapped to linear arrays for various space/time tradeoffs     

Distributed fusion architectures and algorithms for target tracking

Modern surveillance systems often utilize multiple physically distributed sensors of different types to provide complementary and overlapping coverage on targets. In order to generate target tracks and estimates, the sensor data need to be fused. While a centralized processing approach is theoretically optimal, there are significant advantages in distributing the fusion operations over multiple processing nodes. This paper discusses architectures for distributed fusion, whereby each node processes the data from its own set of sensors and communicates with other nodes to improve on the estimates, The information graph is introduced as a way of modeling information flow in distributed fusion systems and for developing algorithms. Fusion for target tracking involves two main operations: estimation and association. Distributed estimation algorithms based on the information graph are presented for arbitrary fusion architectures and related to linear and nonlinear distributed estimation results. The distributed data association problem is discussed in terms of track-to-track association likelihoods. Distributed versions of two popular tracking approaches (joint probabilistic data association and multiple hypothesis tracking) are then presented, and examples of applications are given.     

Resampling algorithms and architectures for distributed particle filters

In this paper, we propose novel resampling algorithms with architectures for efficient distributed implementation of particle filters. The proposed algorithms improve the scalability of the filter architectures affected by the resampling process. Problems in the particle filter implementation due to resampling are described, and appropriate modifications of the resampling algorithms are proposed so that distributed implementations are developed and studied. Distributed resampling algorithms with proportional allocation (RPA) and nonproportional allocation (RNA) of particles are considered. The components of the filter architectures are the processing elements (PEs), a central unit (CU), and an interconnection network. One of the main advantages of the new resampling algorithms is that communication through the interconnection network is reduced and made deterministic, which results in simpler network structure and increased sampling frequency. Particle filter performances are estimated for the bearings-only tracking applications. In the architectural part of the analysis, the area and speed of the particle filter implementation are estimated for a different number of particles and a different level of parallelism with field programmable gate array (FPGA) implementation. In this paper, only sampling importance resampling (SIR) particle filters are considered, but the analysis can be extended to any particle filters with resampling.     

Parallel algorithms/architectures for neural networks

This paper advocates digital VLSI architectures for implementing a wide variety of artificial neural networks (ANNs). A programmable systolic array is proposed, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant to be more general purpose than most other ANN architectures proposed. It may be used for a variety of algorithms in both the retrieving and learning phases of ANNs: e.g., single layer feedback networks, competitive learning networks, and multilayer feed-forward networks. A unified approach to modeling of existing neural networks is proposed. This unified formulation leads to a basic structure for a universal simulation tool and neurocomputer architecture. Fault-tolerance approach and partitioning scheme for large or non-homogeneous networks are also proposed. Finally, the implementations based on commercially available VLSI chips (e.g., Inmos T800) and custom VLSI technology are discussed in great detail.     

Graph-based detection algorithms for layered space-time architectures

We consider a unified framework to develop various graph-based detection algorithms for layered space-time architectures. We start with a factor graph representation for the communication channel, apply a belief propagation (BP) based algorithm for channel detection, and show that the detector achieves a near optimal performance even when number of receive antennas is smaller than number of transmit antennas. Based on this baseline algorithm, we further develop three different extensions of the BP detector that provide a good complexity/performance trade-off, which are especially useful for systems with a large number of antennas or when we encounter a frequency-selective fading channel with a long ISI span. Moreover, all the proposed detectors are soft-input soft-output in nature and they can be directly applied for use in turbo processing without any additional modifications. We study the performance of the new detectors via both simulations and convergence analysis using the measure of average mutual information.     

Optimization of image coding algorithms and architectures usinggenetic algorithms

This paper addresses the application of genetic algorithm (GA)-based optimization techniques to problems in image and video coding, demonstrating the success of GAs when used to solve real design problems with both performance and implementation constraints. Issues considered include problem representation, problem complexity, and fitness evaluation methods. For offline problems, such as the design of two-dimensional filters and filter banks, GAs are shown to be capable of producing results superior to conventional approaches. In the case of problems with real-time constraints, such as motion estimation, fractal search and vector quantization codebook design, GAs can provide solutions superior to those reported using conventional techniques with comparable implementation complexity. The use of GAs to jointly optimize algorithm performance in the context of a selected implementation strategy is emphasized throughout and several design examples are included     

Expression-tree-based algorithms for code compression on embeddedRISC architectures

Reducing program size has become an important goal in the design of modern embedded systems targeted to mass production. This problem has driven efforts aimed at designing processors with shorter instruction formats (e.g., ARM Thumb and MIPS16) or able to execute compressed code (e.g., IBM PowerPC 405), This paper proposes three code compression algorithms for embedded RISC architectures. In all algorithms, the encoded symbols are extracted from program expression trees. The algorithms differ on the granularity of the encoded symbol, which are selected from whole trees, parts of trees, or single instructions. Dictionary-based decompression engines are proposed for each compression algorithm. Experimental results, based on SPEC CINT95 programs running on the MIPS R4000 processor, reveal an average compression ratio of 53.6% (31.5%) if the area of the decompression engine is (not) considered     

Mapping vision algorithms to parallel architectures

Some of the problems encountered in mapping a parallel algorithm are examined, emphasizing mappings of vision algorithms onto mesh, hypercube, mesh-of-trees, pyramid, and parallel random-access machines (PRAMs) having many simple processors, each with a small amount of memory. Approaches that have been suggested include simulating the ideal architectures, and using general data movement operations. Each of these is shown to occasionally produce unacceptably inefficient implementations. It appears that as long as PRAMs cannot achieve the desired cost and performance goals, programmers must contend with carefully designing algorithms for specific architectures     

Binary partition algorithms and VLSI architectures for median andrank order filtering

A class of selection algorithms using binary partition that are very efficient for median and rank order filtering is considered. A unified discussion of these algorithms is presented. The algorithms have better time-area complexity than sorting methods. Counting, firing, and updating are the three basic steps. A generic structure is proposed to realize these algorithms. They can be implemented by simple and regular modules in VLSI     

Schur type algorithms for spatial LS estimation with highlypipelined architectures

A family of Schur-type spatial least-squares algorithms is presented for solving the spatial LS estimation problem, in which the correlation matrix is neither Toeplitz nor near-Toeplitz, by order recursion. Normalized spatial Levinson- and Schur-type algorithms are also derived. Highly pipelined architectures are designed to realize these recursions. The reflection coefficients are first computed using the spatial Schur type recursions. Then, the forward and backward filter parameters are calculated by the spatial Levinson-type recursions. A pyramid systolic array is demonstrated to calculate not only the filter parameters but also the LDU decomposition of the inverse cross-correlation matrix at every clock phase. This pyramid array can be mapped onto a two-dimensional systolic array which has a simpler structure. A square systolic array is developed to implement the Levinson- and Schur-type temporal recursive LS (RLS) algorithms. A highly concurrent architecture which exploits the parallelism of the spatial Schur-type recursions is illustrated to perform the LDU decomposition of the cross-correlation matrix     

Real-time algorithms and architectures for multiuser channelestimation and detection in wireless base-station receivers

This paper presents algorithms and architecture designs that can meet real-time requirements of multiuser channel estimation and detection in future code-division multiple-access-based wireless base-station receivers. Sophisticated algorithms proposed to implement multiuser channel estimation and detection make their real-time implementation difficult on current digital signal processor-based receivers. A maximum-likelihood based multiuser channel estimation scheme requiring matrix inversions is redesigned from an implementation perspective for a reduced complexity, iterative scheme with a simple fixed-point very large scale integration (VLSI) architecture. A reduced-complexity, bit-streaming multiuser detection algorithm that avoids the need for multishot detection is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for multiuser channel estimation and detection for third-generation wireless systems by: (1) designing the algorithms from a fixed-point implementation perspective, without significant loss in error rate performance; (2) task partitioning; and (3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, parallelism, and bit-level computations to achieve real-time with minimum area overhead     

Efficient hybrid tree/linear array architectures for block-matchingmotion estimation algorithms

Execution latency and I/O bandwidth play essential roles in determining the effectiveness and the cost of a parallel hardware implementation for block-matching motion estimation algorithms. Unfortunately, almost all traditional architecture designs, e.g. the two-dimensional mesh-connected systolic array architecture (2DMCSA) and the tree-type structure (TTS), fail to take these two factors into account simultaneously. As a result, they suffer from either large execution latency or huge input bandwidth requirements. The authors propose a family of tree/linear architectures, which efficiently optimise the total implementation cost by combining the merits of the 2DMCSA and the TTS. Moreover, to facilitate hardware designs, the authors present the tree-cut techniques and the on-chip buffer design method to meet computational demands various video compression applications. The proposed architectures are capable executing the exhaustive search and the search block-matching algorithms, they offer relatively flexible and cost-effective hardware solutions for a wide range of video coding systems, including CD-ROM, portable visual communications systems and high-definition TV     

On generating distributed intelligence systems architectures usinggenetic algorithms

A methodology for generating large scale distributed intelligence systems (DIS's) using genetic algorithms is presented. An organizational structure (chromosome) is characterized by generic interactions (genes) among the individual nodes comprising it. The objective function evaluates each structure in the generated population against a set of structural constraints and some user defined criteria. The structures satisfying these constraints are feasible solutions to the design problem     

VLSI algorithms and architectures for complex householder transformation with applications to array processing

The Householder transformation is considered to be desirable among various unitary transformations due to its superior computational efficiency and robust numerical stability. Specifically, the Householder transformation outperforms the Givens rotation and the modified Gram-Schmidt methods in numerical stability under finite-precision implementations, as well as requiring fewer arithmetical operations. Consequently, the QR decomposition based on the Householder transformation is promising for VLSI implementation and real-time high throughput modern signal processing. In this paper, a recursive complex Householder transformation (CHT) with a fast initialization algorithm is proposed and its associated parallel/pipelined architecture is also considered. Then, a CHT based recursive least-squares algorithm with a fast initialization is presented. Its associated systolic array processing architecture is also considered.This work was supported in part of the National Science Council of the R.O.C. under grant NSC80-E-SP-009-01A.This work was supported in part by a UC Micro grant and NSF grant NCR-8814407.     

基于AI和O-RAN架构的5G网络容量自适应算法

移动运营商目前正面临流量爆发式增长和增量不增收的双重困境,需求、投资和效能三者处于不均衡状态。5G的到来为网络能力与用户需求的匹配提供了新的解决方案,O-RAN新架构可以有效引入近年来人工智能领域的各项研究成果,在有限的资源下更好地为用户提供服务。基于AI大数据技术对基站容量空时特征分析形成的精准预测,可以指导网络建设、优化和维护资源的投放、形成容量自适应的弹性网络,使得网络能力和用户需求紧密耦合,达到提高资源配置精准性和提升网络资源利用率的目标。     

Ethernet passive optical network architectures and dynamic bandwidth allocation algorithms

We compile and classify the research work conducted for Ethernet passive optical networks. We examine PON architectures and dynamic bandwidth allocation algorithms. Our classifications provide meaningful and insightful presentations of the prior work on EPONs. The main branches of our classification of DBA are: grant sizing, grant scheduling, and optical network unit queue scheduling. We further examine the topics of QoS support, as well as fair bandwidth allocation. The presentation allows those interested in advancing EPON research to quickly understand what already was investigated and what requires further investigation. We summarize results where possible and explicitly point to future avenues of research.