氮注入多晶硅栅对超薄SiO2栅介质性能的影响

p+多晶硅栅中的硼在SiO2栅介质中的扩散会引起栅介质可靠性退化,在多晶硅栅内注入N+的工艺可抑制硼扩散.制备出栅介质厚度为4.6nm的p+栅MOS电容,通过SIMS测试分析和I-V、C-V特性及电应力下击穿特性的测试,观察了多晶硅栅中注N+工艺对栅介质性能的影响.实验结果表明:在多晶硅栅中注入氮可以有效抑制硼扩散,降低了低场漏电和平带电压的漂移,改善了栅介质的击穿性能,但同时使多晶硅耗尽效应增强、方块电阻增大,需要折衷优化设计.     

多晶硅注氮制备4.6nm超薄栅介质

为了改善深亚微米CMOS器件p+-poly栅中硼扩散问题,通过选择合适的注氮能量和剂量,采用多晶硅栅注氮工艺,既降低了硼在多晶硅栅电极中的扩散系数,又在栅介质内引入浓度适宜的氮,有效地抑制了硼在栅介质内的扩散所引起的平带电压漂移,改善了Si/SiO2界面质量,提高了栅介质和器件的可靠性,制备出了性能良好的4.6nm超薄栅介质.     

多晶硅注氮制备4.6nm超薄栅介质

为了改善深亚微米CMOS器件p+ - poly栅中硼扩散问题,通过选择合适的注氮能量和剂量,采用多晶硅栅注氮工艺,既降低了硼在多晶硅栅电极中的扩散系数,又在栅介质内引入浓度适宜的氮,有效地抑制了硼在栅介质内的扩散所引起的平带电压漂移,改善了Si/Si O2 界面质量,提高了栅介质和器件的可靠性,制备出了性能良好的4 .6 nm超薄栅介质.     

硼扩散引起薄SiO2栅介质的性能退化

采用表沟p+多晶硅栅/PMOSFET代替埋沟n+多晶硅栅/PMOSFET具有易于调节阈值电压、降低短沟效应和提高器件开关特性的优点,因而在深亚微米CMOS工艺中被采纳.但是多晶硅掺杂后的高温工艺过程会使硼杂质扩散到薄栅介质和沟道区内,引起阈值电压不稳定和栅介质击穿性能变差.迄今为止对硼扩散退化薄栅介质可靠性的认识并不是很明朗,为此本文考察了硼扩散对薄栅介质击穿电荷和Fowler-Nordheim (FN)电应力产生SiO2/Si界面态的影响.     

离子注入氮化薄SiO2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化10nm薄栅SiO2的特性.实验证明氮化后的薄SiO2栅具有明显的抗硼穿透能力,它在FN应力下的氧化物陷阱电荷产生速率和正向FN应力下的慢态产生速率比常规栅介质均有显著下降,氮化栅介质的击穿电荷(Qbd)比常规栅介质提高了20%.栅介质性能改善的可能原因是由于离子注入工艺在栅SiO2中引进的N+离子形成了更稳定的键所致.     

离子注入氮化薄SiO_2栅介质的特性

研究了通过多晶硅栅注入氮离子氮化 10 nm薄栅 Si O2 的特性 .实验证明氮化后的薄 Si O2 栅具有明显的抗硼穿透能力 ,它在 FN应力下的氧化物陷阱电荷产生速率和正向 FN应力下的慢态产生速率比常规栅介质均有显著下降 ,氮化栅介质的击穿电荷 (Qbd)比常规栅介质提高了 2 0 % .栅介质性能改善的可能原因是由于离子注入工艺在栅 Si O2 中引进的 N+离子形成了更稳定的键所致     

3.4nm超薄SiO2栅介质的特性

用LOCOS工艺制备出栅介质厚度为3.4nm的MOS电容样品,通过对样品进行I-V特性和恒流应力下V-t特性的测试,分析用氮气稀释氧化法制备的栅介质的性能,同时考察了硼扩散对栅介质性能的影响.实验结果表明,制备出的3.4nm SiO₂栅介质的平均击穿场强为16.7MV/cm,在恒流应力下发生软击穿,平均击穿电荷为2.7C/cm².栅介质厚度相同的情况下,P⁺栅样品的击穿场强和软击穿电荷都低于N⁺栅样品.     

多晶硅栅的BCl离子注入技术

在CMOS中,有n—MOS和P—MOS两种晶体管。为了简化制造工艺,在制作多晶硅栅时,最好先都制成n~+多晶硅,然后再对P—MOS管栅的n~+多晶硅注入B~+,使其变成p~+型多晶硅。可是,随着集成度的提高,最小线宽越变越窄,也要求多晶硅膜更薄,即使用很低能量的B~+来注入,B~+也会穿透多晶硅层进入基片中。为避免穿透,已发展了采用BF_2~+注入来形成P~+型多晶硅栅的办法。它确实能有效地降低B的注入深度,但也带来了另外的问题,这就是BF_2~+注入多晶硅中的F元素,在氧化膜中扩散,在随后的热处理中,会使氧化膜中B加速扩散到基片中,引起V_(TH)的变化,而成为一个麻烦问题。     

离子注入氮化薄SiO2栅介质的特性

研究了通过多晶硅栅洲入氮离子氮化10nm薄栅SiO2的特性,实验证明氮化后的薄SiO2栅具有明显的抗硼穿透能力,它在FN应力下的氧化物陷阱电荷产生速率和正向FN应力下的慢态产生速率比常规栅介均有显下降,氮化栅介质的击穿电荷（Qbd)比常规栅介质提高了20％,栅介质性能的可能原因是由于离子注入工艺在栅SiO2中引进的N^ 离子形成了更稳定的键所致。     

基于双栅PMOSFET模型的硼穿通分析方法

随着栅氧化层厚度的不断减小,硼穿通问题变得越来越严重.特别是在表面沟道器件中,非常容易出现硼穿通现象.为了减小P型多晶硅栅电极中硼穿通的影响,需要明确多晶硅栅电极中硼穿通与栅氧化层厚度之间的关系.提出的双栅PMOSFET模型将P型多晶硅栅极与N型多晶硅栅极的功函数之差与阈值电压差值进行对比,完成了硼穿通的判定.通过优化热氧化条件,采用N2O热处理,能够有效改善薄栅氧化层PMOSFET中的硼穿通问题.     

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode of PMOS devices

PMOS devices with different amounts of nitrogen implanted into the gate electrode before doping with BF₂ implantation and implant anneal were manufactured. The thicknesses of the gate oxides grown in dry oxygen by RTP were 4.1 down to 2.8 nm. The implant anneal was also performed by RTP. The influence of the nitrogen on the penetration of boron ions through the ultra-thin gate oxides into the channel region was investigated by electrical and SIMS measurements. Boron was effectively prevented from diffusion by high nitrogen concentrations at the polysilicon/gate oxide interface without degrading the reliability. In return, increased sheet resistivities and gate depletion have to be taken into account by high nitrogen concentrations within the polysilicon gate electrode.     

Gate engineering for deep-submicron CMOS transistors

Gate depletion and boron penetration through thin gate oxide place directly opposing requirements on the gate engineering for advanced MOSFET's. In this paper, several important issues of deep-submicron CMOS transistor gate engineering are discussed. First, the impact of gate nitrogen implantation on the performance and reliability of deep-submicron CMOSFET's is investigated. The suppression of boron penetration is confirmed by the SIMS profiles, and is attributed mainly to the diffusion retardation effect in bulk polysilicon by the presence of nitrogen. The MOSFET' I-V characteristics, MOS capacitor quasi-static C-V curves, SIMS profiles, gate sheet resistance, and oxide Q_bd are compared for different nitrogen implant conditions. A nitrogen dose of 5×10¹⁵ cm^-2 is found to be the optimum choice at an implant energy of 40 keV in terms of the overall electrical behavior of CMOSFET's. Under optimum design, gate nitrogen implantation is found to be effective in eliminating boron penetration without degrading performance of either p⁺ gate p-MOSFET and n⁺ gate n-MOSFET. Secondly, the impact of gate microstructure on the performance of deep-submicron CMOSFET's is discussed by comparing poly and amorphous silicon gate deposition technologies. Thirdly, poly-Si_1-xGe_x is presented as a superior alternative gate material. Higher dopant activation efficiently results in higher active-dopant concentration near the gate/SiO₂ interface without increasing the gross dopant concentration. This plus the lower annealing temperature suppress the dopant penetration. Phosphorus-implanted poly-Si_1-xGe_x is gate is compared with polysilicon gate in this study     

Suppression of boron penetration through thin gate oxides by nitrogen implantation into the gate electrode in PMOS devices

PMOS devices with and without nitrogen implant into the gate electrode before doping with boron and with nitridation of the gate oxide were manufactured. The influence of nitrogen on the penetration of boron ions into the substrate through ultra-thin gate oxides was investigated by electrical and SIMS measurements. Boron diffusion can be effectively prevented by high nitrogen concentrations located immediately above the gate oxide and within the polysilicon gate electrode.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

超薄Si3N4/SiO2叠层栅介质可靠性研究

实验成功地制备出等效氧化层厚度为亚2nm的Nitride/Oxynitride(N/O)叠层栅介质难熔金属栅电极PMOS电容并对其进行了可靠性研究.实验结果表明相对于纯氧栅介质而言,N/O叠层栅介质具有更好的抗击穿特性,应力诱生漏电特性以及TDDB特性.进一步研究发现具有更薄EOT的难熔金属栅电极PMOS电容在TDDB特性以及寿命等方面均优于多晶硅栅电极的相应结构.     

两种注F层面的PMOSFET电离辐射响应特性

报道了栅氧化淀积多晶硅前后分别注入43keVF离子的Si栅P沟MOSFET电离辐射响应关系。结果发现,多晶硅面注F具有较强的抑制辐射感生阈电压漂移,控制氧化物电荷和界面态生长的能力。用多晶硅面注F带入栅介质较少注入缺陷和较多替代辐射敏感应力键的F离子模型对实验结果进行了讨论。     

Gate length dependent polysilicon depletion effects

Degradation of MOS gate capacitance in the inversion region becomes worse as the gate length is scaled down, according to a new experiment. Namely, the polysilicon depletion effect has gate length dependence. The origin of this gate length-dependent polydepletion effect has been modeled and verified by using device simulation. As a result, the gradient of dopant distribution resulting from ion implantation is shown to be an additional potential drop in the polygate. In addition, the enlarged depletion width at the gate sidewall can worsen the polydepletion effect for very-small MOSFETs     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高3nm栅氧W/TiN叠层栅MOS电容的性能.实验选取了合适的TiN厚度来减小应力,以较小的TiN溅射率避免溅射过程对栅介质的损伤,并采用了较高的N2/Ar比率在TiN溅射过程中进一步氮化了栅介质.实验得到了高质量的C-V曲线,并成功地把Nss(表面态密度)降低到了8×1010/cm2以下,达到了与多晶硅栅MOS电容相当的水平.     

Gate capacitance attenuation in MOS devices with thin gatedielectrics

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the silicon and polysilicon electrodes. For the first time, we quantitatively explore the combined impact of degenerate carrier statistics, quantum effects, and the semiconducting nature of the gate electrode on gate capacitance. Only by including all of these effects can we successfully model the capacitance-voltage behavior of sub-10 nm MOS capacitors. For typical devices, we find the gate capacitance to be 10% less than the oxide capacitance, but it can be attenuated by 25% or more for 4 nm oxides with polysilicon gates doped to less than 10²⁰ cm^-3