基于无冲突多项式交织器的高速并行Turbo解码器

提出了基于高次多项式无冲突交织器的Turbo码并行解码的优化实现方法,解码器采用MAX-Log-MAP算法,完成了从Matlab算法设计验证到RTL设计、FPGA验证,并在LTE无线通信链路中验证.设计的Turbo并行高速解码器半次迭代的效率为6.9 bit/cycle,在最高迭代为5.5次、时钟频率为309MHz下,达到207Mb/s的吞吐率,满足高速无线通信系统的要求,交织和解交织采用存储器映射方法.该设计节约了计算电路和存储量.     

多制式音频解码系统中IMDCT算法优化与硬件实现

逆改良型离散余弦变换(IMDCT)是高质量音频解码器的基本处理单元,其运算中大量的乘法是实现高效IMDCT的一个瓶颈.通过优化IMDCT的算法,实现了一个高效的IMDCT硬件加速器,具有很好的可配置功能,可支持12点,36点及2的幂次点数的IMDCT.通过蝶形拆分运算加快了解码速度,同时通过一个乘法器的复用,大大地降低了解码器的面积.     

CCSDS标准的Turbo译码器的硬件设计

Turbo码具有接近Shannon信道理论极限的译码性能,CCSDS在保留原编码方案的前提下已将其加入遥测信道编码建议书。在简要介绍CCSDS标准的编码结构以后,概述了相应的Turbo码译码器的硬件设计方案。详细介绍了具体的设计流程,最后给出了设计结果。     

改进Turbo码译码器硬件实现的方法

简要描述了基于Log-MAP译码算法的MAP译码器结构,介绍了几种改善其硬件实现结构的途径:选择合理的计算顺序和进行适当简化方法;引入了滑动窗方法;给出了通过改变数据存储结构来减小存储器的大小的方法。分析了改进方法对译码性能和实现的影响。     

Reconfigurable Parallel Turbo Decoder Design for Multiple High-Mobility 4G Systems

For high-mobility 4G applications of LTE-A and WiMAX-2 systems, this paper presents a dual-standard turbo decoder design with the following three techniques. 1) Circular parallel decoding reduces decoding latency and improves throughput rate. 2) Collision-free vectorizable dual-standard parallel interleaver enhances hardware utilization of the interleaving address generator. 3) One-bank extrinsic buffer design with bit-level extrinsic information exchange reduces size of the extrinsic buffer compared with the two-bank extrinsic buffer design. Furthermore, a multi-standard turbo decoder chip is fabricated in a core area of 3.38 mm² by 90 nm CMOS process. This chip is maximally measured at 152 MHz with 186.1 Mbps for LTE-A standard and 179.3 Mbps for WiMAX-2 standard.     

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.      

Efficient Memory Architecture and Implementation of Motion Compensation for Multi-Standard Video Decoder

设计了一种适用于多标准视频解码器的存储架构,采用并行多级流水线用以实现AVS,MPEG -2,H.264标准中不同模式的图像预测计算,缓存机制避免了频繁访问外部存储器SDRAM,提高了运动补偿计算性能,减少了计算周期.使用90nm的CMOS工艺库,在135 MHz的工作频率下综合,电路规模为45 kgate(千门)左右,处理一宏块需要大约520个时钟周期,结果表明该设计满足高清视频处理的要求.     

基于DSP实现的8状态turbo码译码器

国际电信联合会在UMTS/3GPP规范中推荐8状态turbo码作为数据纠错的方案。本文回顾了turbo码的MAX-LOG-MAP译码算法,并分析了输入量化方式对译码性能的影响。在100MHz的定点DSP芯片上实现该算法时,译码速度达到110kbps～300kbps。     

Turbo译码器的log_MAP算法及其实现

首先讲述了Turbo编译码的原理,然后主要对Turbo译码的最大后验概率(MAP)算法演化而来的可实现的log_MAP译码算法进行了研究。最后讨论了log_MAP算法在数字信号处理器(DSP)中的实现。     

基于FPGA的双二进制Turbo译码器的硬件实现

针对宽带电力载波通信中采用的双二进制Turbo译码器,给出了一种基于FPGA的并行实现方案。该方案采用无交叠滑动窗的多路并行分块以及流水线结构,以Xilinx的XC7K410T为硬件平台,采用Verilog硬件描述语言来设计实现,给出了不同并行块数的实现结果。当数据块长为520字节时,4次迭代后,数据速率可达200 Mbit/s。测试结果表明,该方案占用资源少、译码速度快、性能指标满足要求,具有较好的应用价值。     

卷积Turbo码logMAP的DSPs实现

在详细研究卷积Turbo码的logMAP算法的基础上，根据DSP(TMS320CA201)的硬件特点实现了IEEE802．16标准中的Turbo译码器。     

Design of Prunable Interleavers for Parallel Turbo Decoder Architectures

In this paper we propose a technique to implement in a parallel fashion a turbo decoder based on an arbitrary permutation, and to expand its interleaver in order to produce a family of prunable S-random interleavers suitable for parallel implementations. We show that the spread properties of the obtained interleavers are almost optimal and we prove by simulation that they are very competitive in terms of error floor performance. A few details on the decoder architecture are also provided     

基于定点DSP的Turbo码译码器实现

在介绍了一种改进的Max—Log-MAP译码算法基础上．讨论了与定点DSP实现译码算法相关的量化精度、溢出处理及数据存储等几个问题,并采用VC5409实现了（13．15）8Turbo码译码器．经测试．其性能接近浮点译码性能．     

Implementation of a High Throughput 3GPP Turbo Decoder on GPU

Turbo code is a computationally intensive channel code that is widely used in current and upcoming wireless standards. General-purpose graphics processor unit (GPGPU) is a programmable commodity processor that achieves high performance computation power by using many simple cores. In this paper, we present a 3GPP LTE compliant Turbo decoder accelerator that takes advantage of the processing power of GPU to offer fast Turbo decoding throughput. Several techniques are used to improve the performance of the decoder. To fully utilize the computational resources on GPU, our decoder can decode multiple codewords simultaneously, divide the workload for a single codeword across multiple cores, and pack multiple codewords to fit the single instruction multiple data (SIMD) instruction width. In addition, we use shared memory judiciously to enable hundreds of concurrent multiple threads while keeping frequently used data local to keep memory access fast. To improve efficiency of the decoder in the high SNR regime, we also present a low complexity early termination scheme based on average extrinsic LLR statistics. Finally, we examine how different workload partitioning choices affect the error correction performance and the decoder throughput.     

串行Turbo译码器窗口二分法改进与FPGA实现

提出了一种比滑动窗算法更为有效的窗口二分法,该算法在相同译码参数情况下比滑动窗时序节省更多的时间,同时消除了滑动窗时序所带来的码性能下降,将该算法应用于串行译码中,通过Matlab仿真,并用Vefilog语言硬件化,在Xilinx公司的XC3S 1500 FPGA上实现.结果表明,该算法降低了译码时延,并保证了码性能.     

3G系统中Turbo译码改进及DSP实现

由于Turbo码优异的纠错性能,使其在第三代移动通信系统中倍受重视。为了解决Turbo码存在的译码复杂度大、译码延时长的缺点,在分析已有的Max-Log-Map码译码算法基础上,针对DSP的特点进行改进,提出加入滑动窗和改进的归一化度量算法,在保证译码性能的前提下,大大降低其运算复杂度,并将滑动窗的方法用于译码模块,极大的减少了存储空间。     

一种全并行LDPC译码器及FPGA实现方法

低密度校验(Low-Density Parity-Check)码作为迄今为止性能接近香农限的前向纠错码(FEC)之一,在无线通信、卫星通信和无线网络技术等领域获得了广泛的应用。随着 5G 技术的发展,通信系统对传输速率的需求逐渐增加,更高的传输速率对 LDPC 译码器的吞吐量提出了更高的要求。本文给出了一种全并行 LDPC 译码器设计,并采用理论分析和仿真结果分析相结合的方法,对 LDPC 码的并行译码方法进行了研究,给出了全并行译码器的 FPGA 实现方法。     

LDPC码的全并行概率译码

针对LDPC码和积译码算法运算量大、电路实现复杂度高,介绍一种新的LDPC译码实现结构——概率译码器。该结构结合随机运算思想,运算量大幅降低,电路布线实现压力减小,吞吐量显著提高,针对该算法的内部路由可能出现的死锁问题引入了边存储器（EM,Edge Memory）概念。在AWGN信道下,对上述方法进行了仿真验证,给出了新方案和旧算法的性能分析比较,结果显示该算法的性能相比传统LDPC译码器有近0.2 dB的性能损失,但译码复杂度得到显著降低。     

TD-SCDMA终端系统384 kbps Turbo 码译码解决方案

本文在分析已有的Turbo码译码算法的基础上提出了TD-SCDMA终端系统384kbpsTurbo码译码器的实现结构和方法,并通过FPGA进行硬件实现,给出了实现的资源占用和译码性能,证明该实现方法具有很高的经济意义和实用意义。     

帧长可配置Turbo码编译码器的设计与实现

针对固定帧长Turbo码灵活性和适应性差的缺点,提出了一种帧长可配置的Turbo码编 译码器的FPGA实现方案,可以由用户根据数字通信参数设计要求自行改变交织深度, 以使译码性能与信息速率达到最佳平衡。采用“自上而下”的设计思想和“自下而上” 的实现流程相结合的方法,对Turbo码编译码系统进行模块化设计,优化调试后下载配置到X ilinx公司的Virtex-2 Pro系列中。测试结果表明,该设计具有良好的移植性和通用性,为T urbo码在不同环境下的应用建立了统一平台。