Architectural strategies for low-power VLSI turbo decoders

The use of "turbo codes" has been proposed for several applications, including the development of wireless systems, where highly reliable transmission is required at very low signal-to-noise ratios (SNR). The problem of extracting the best coding gains from these kind of codes has been deeply investigated in the last years. Also the hardware implementation of turbo codes is a very challenging topic, mainly due to the iterative nature of the decoding process, which demands an operating frequency much higher than the data rate; in the case of wireless applications, the design constraints became even more strict due to the low-cost and low-power requirements. This paper first presents a new architecture for the decoder core with improved area and power dissipation properties; then partitioning techniques are proposed to reduce the power consumption of the decoder memories. It is proven that most of the power is dissipated by the large RAM units required by the decoder, so the described technique is very efficient: an average power saving of 70% with an area overhead of 23% has been obtained on a set of analyzed architectures.     

Area-efficient high-speed decoding schemes for turbo decoders

Turbo decoders inherently have large decoding latency and low throughput due to iterative decoding. To increase the throughput and reduce the latency, high-speed decoding schemes have to be employed. In this paper, following a discussion on basic parallel decoding architectures, the segmented sliding window approach and two other types of area-efficient parallel decoding schemes are proposed. Detailed comparison on storage requirement, number of computation units, and the overall decoding latency is provided for various decoding schemes with different levels of parallelism. Hybrid parallel decoding schemes are proposed as an attractive solution for very high level parallelism implementations. To reduce the storage bottleneck for each subdecoder, a modified version of the partial storage of state metrics approach is presented. The new approach achieves a better tradeoff between storage part and recomputation part in general. The application of the pipeline-interleaving technique to parallel turbo decoding architectures is also presented. Simulation results demonstrate that the proposed area-efficient parallel decoding schemes do not cause performance degradation.     

High performance parallel turbo decoder with configurable interleaving network for LTE application

In this paper, a high performance parallel turbo decoder is designed to support 188 block sizes in the 3rd generation partnership (3GPP) long term evolution (LTE) standard. A novel configurable quadratic permutation polynomial (QPP) multistage network and address generator are proposed to reduce the complexity of interleaving. This 2ⁿ-input network can be configured to support any 2ⁱ-input $(0\le i\le n)$ network. Furthermore, it can flexibly support arbitrary contention-free interleavers by cascading an additional specially designed network. In addition, an optimized decoding schedule scheme is presented to reduce the performance loss caused by high parallelism. Memory architecture and address mapping method are optimized to avoid memory access contention of small blocks. Moreover, a dual-mode add–compare–select (ACS) unit implementing both radix-2 and radix-4 recursion is proposed to support the block sizes that are not divided by 16. Implemented in 130 nm CMOS technology, the design achieves 384.3 Mbps peak throughput at clock rate of 290 MHz with 5.5 iterations. Consuming 4.02 mm² core area and 716 mW power, the decoder has a 1.81 bits/cycle/iteration/mm² architecture efficiency and a 0.34 nJ/bit/iteration energy efficiency, which is competitive with other recent works.     

一种新型的turbo码LOG-MAP译码算法

给出了一种新型的turbo码LOC-MAP译码算法，相对于传统的LOG-MAP译码算法，主要有两点创新。其一，对于LOC-MAP算法中的校正函数采用三阶Newton插值函数拟合，相对于分段线性函数拟合，省去了查找表过程和查找表的存储；其二，相对于传统的单滑动窗口技术，采用双滑动窗口技术，对于前向递归和后向递归分别采用滑动窗口技术，同时采用预处理技术，这样显著地提高了译码速度。     

Low complexity decision-aided decoder for turbo DPSK

A new decision-aided soft a posteriori probability (APP) algorithm for iterative differential phase-shift keying (DPSK) signal demodulation/decoding in a Rayleigh flat-fading channel is presented. Compared with conventional APP algorithms for iterative DPSK, the new algorithm results in considerably lower decoding cost yet can achieve nearly the same performance     

High-performance VLSI architectures for turbo decoders with QPP interleaver

This paper analyses different VLSI architectures for 3GPP LTE/LTE-advanced turbo decoders for trade-offs in terms of throughput and area requirement. Data flow graphs for standard SISO MAP (maximum a posteriori) turbo decoder, SW – SISO MAP turbo decoder, PW SISO MAP turbo decoder have been presented, thus analysing their performance. Two variants of quadratic permutation polynomial (QPP) interleaver have been proposed which tend to simplify the complexity of ‘mod’ operator implementation and provide best compromise between area, delay and power dissipation. Implementation of decoder using one variant of QPP interleaver has also been discussed. A novel approach for area optimisation has been proposed to reduce required number of interleavers for parallel window turbo decoder. Multi-port memory has also been used for parallel turbo decoder. To increase the throughput without any effective increase in area complexity, circuit-level pipelining and retiming have been used. Proposed architectures have been synthesised using Synopsys Design Compiler using 45-nm CMOS technology.     

An efficient Chase decoder for turbo product codes

In this letter, we propose an efficient decoding algorithm for turbo product codes as introduced by Pyndiah. The proposed decoder has no performance degradation and reduces the complexity of the original decoder by an order of magnitude. We concentrate on extended Bose-Chaudhuri-Hocquengem codes as the constituent row and column codes because of their already low implementation complexity. For these component codes, we observe that the weight and reliability factors can be fixed, and that there is no need for normalization. Furthermore, as opposed to previous efficient decoders, the newly proposed decoder naturally scales with a test-pattern parameter p that can change as a function of iteration number, i.e., the efficient Chase algorithm presented here uses conventionally ordered test patterns, and the syndromes, even parities, and extrinsic metrics are obtained with a minimum number of operations.     

A hybrid neural network model for predicting silicon content

The silicon content of the hot metal in the blast furnace ironmaking process normally reflects the thermal state of the furnace and affects the fuel rate. In this paper a hybrid neural network model is proposed to predict the silicon contentn steps ahead. A time-delay neural network, which has self-loops to represent dynamics, is adopted here. The learning procedure of this network has been divided into two states. A BP algorithm with forgetting factor is first introduced to find the appropriate structure of the network. The temporal difference (TD) method with forgetting factor is then used forn-step-ahead prediction. The results show that the method can perform satisfactoryn-step-ahead prediction and is suited for implementation.     

Variable-size interleaver design for parallel turbo decoder architectures

In this paper, we propose two techniques to design good S-random interleavers, to be used in parallel and serially concatenated codes with interleavers. The interleavers designed according to these algorithms can be shortened, in order to support different block lengths in such a way that all the permutations obtained by pruning, when employed in a parallel turbo decoder, are collision-free. The first technique, suitable for short and medium interleavers, guarantees the same performance of nonparallel interleavers in terms of spreading properties, simulated frame-error probabilities, and obtainable minimum distance of the actual codes. The second algorithm, to be used for large block lengths, permits achieving high degrees of parallelism at the price of a slight degradation of the spread properties, and also to change the degree of parallelism on-the-fly. The operations of a parallel turbo decoder employing these interleavers are described, and an example of the advantages of the proposed techniques is provided in a realistic system framework.     

A parallel decoder for low latency decoding of turbo product codes

There has been intensive focus on turbo product codes (TPCs) which have low decoding complexity and achieve near-optimum performances at low signal-to-noise ratios. Different than the original TPC decoder, which performs row and column decoding in a serial fashion, we propose a parallel decoder structure. Simulation results show that with this approach, decoding latency of TPCs can be halved while maintaining virtually the same performance level     

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.     

A low power turbo/Viterbi decoder for 3GPP2 applications

This paper presents a channel decoder that completes both turbo and Viterbi decodings, which are pervasive in many wireless communication systems, especially those that require very low signal-to-noise ratios. The trellis decoding algorithm merges them with less redundancy. However, the implementation is still challenging due to the power consumption in wearable devices. This research investigates an optimized memory scheme and rescheduled data flow to reduce power consumption and chip area. The memory access is reduced by buffering the input symbols, and the area is reduced by reducing the embedded interleaver memory. A test chip is fabricated in a 1.8 V 0.18-/spl mu/m standard CMOS technology and verified to provide 4.25-Mb/s turbo decoding and 5.26-Mb/s Viterbi decoding. The measured power dissipation is 83 mW, while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block. The power consumption in Viterbi decoding is 25.1 mW in the 1-Mb/s data rate. The measurement shows the power dissipation is 83 mW for the turbo decoding with six iterations at 3.1 Mb/s, and 25.1 mW for the Viterbi decoding at 1 Mb/s.     

Application of neural network inverse control system in turbo decoding

Adaptive inverse control system can improve the performance of turbo decoding, and modeling turbo decoder is one of the most important technologies. A neural network model for the inverse model of turbo decoding is proposed in this paper. Compared with linear filter with its revision, the general relationship between the input and output of the inverse model of turbo decoding system can be established exactly by Nonlinear Auto-Regressive eXogeneous input （NARX） filter. Combined with linear inverse system, it has simpler structure and costs less computation, thus can satisfy the demand of real-time turbo decoding. Simulation results show that neural network inverse control system can improve the performance of turbo decoding further than other linear control system.     

Research on fuzzy neural network algorithms for nonlinear network traffic predicting

Neural networks provide massive parallelism,robust-ness ,and approxi mate reasoning,which are i mportantfor dealing with uncertain,inexact ,and ambiguous data,withill-defined problems and sparse data sets[1].It hasbeen proved that a neural network system …     

The design and performance of a neural network for predicting turbodecoding error with application to hybrid ARQ protocols

It is shown that a neural network can be trained to observe the cross entropy of the outputs of component decoders in a turbo error control system and to accurately predict the presence of errors in the decoded data. The neural network can be used as a trigger for retransmission requests at either the beginning or the conclusion of the decoding process, providing improved reliability and throughput performance at a lower average decoding complexity than turbo decoding with cyclic redundancy check error detection     

A low complexity block turbo decoder architecture - [transactions letters]

In this letter we present a low-complexity architecture designed for the decoding of block turbo codes. In particular we simplify the implementation of Pyndiah?s algorithm by not storing any of the concurrent codewords generated by the list decoder.     

On the probability of symbol error in Viterbi decoders

An upper bound is derived on the probability that at least one of a sequence of B consecutive bits at the output of a Viterbi (1979) decoder is in error. Such a bound is useful for the analysis of concatenated coding schemes employing an outer block code over GF(2^B) (typically a Reed-Solomon (RS) code), an inner convolutional code, and a symbol (GF(2^B)) interleaver separating the two codes. The bound demonstrates that in such coding schemes a symbol interleaver is preferable to a bit interleaver. It also suggests a new criterion for good inner convolutional codes     

A contribution to the reduction of the dynamic power dissipation in the turbo decoder

In the field of mobile communication systems, the energy issue of a turbo decoder becomes an equivalent constraint as throughput and performance. This paper presents a contribution to the reduction of the power consumption in the turbo decoder. The main idea is based on re-encoding technique combined with dummy insertion during the iterative decoding process. This technique, named “toward zero path” (TZP) helps in reducing the state transition activity of the Max-Log-MAP algorithm by trying to maintain the survivor path on the ‘zero path’ of the trellis. The design of a turbo decoder based on the TZP technique, associated with different power reduction technique (saturation of state metrics, stoping criterium) is described. The resulting turbo decoder was implemented onto a Xilinx VirtexII-Pro field-programmable gate array (FPGA) in a digital communication experimental setup. Performance and accurate power dissipation measurements have been done thanks to dynamic partial reconfiguration of the FPGA device. The experimental results have shown the interest of the different contributions for the design of turbo decoders.     

On the performance/complexity tradeoff in block turbo decoder design

In this letter, tradeoffs between very large scale integration implementation complexity and performance of block turbo decoders are explored. We address low-complexity design strategies on choosing the scaling factor of the log extrinsic information and on reducing the number of hard-decision decodings during a Chase search.     

Turbo码编码FDPIM在弱湍流下的差错性能分析

DPIM调制方式的符号长度变化不固定,分析Turbo码编码DPIM调制下的差错性能存在的困难,针对该问题给出了一种新的调制方式--定长脉冲间隔调制.在给出其调制结构的基础上,在弱湍流信道模型下首先推导分析了未编码FDPIM的误包率,并与DPIM 调制方式的性能进行了比较,然后分别采用三种模型分析了Turbo编码FDPIM调制的误比特率特性.仿真分析结果表明,未编码下的FDPIM的误包率虽然劣于DPIM,但其实现的复杂性简化,相对于DPIM,其符号长度固定,易与Turbo码译码结构相结合实现软判决;在该调制方式下引入Turbo码可使平均发射功率降低约10 dBm,能够有效的改善系统差错性能.