共查询到20条相似文献,搜索用时 171 毫秒
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低功耗无线传感器网络节点的设计 总被引:1,自引:1,他引:0
文章分析了传感器节点的能耗,介绍了一种采用MSP430F149处理器和无线收发模块设计的低功耗无线传感器网络节点,阐述了该节点的组成、节点处理控制单元、无线通信单元和传感探测单元的设计及节点软件的设计等。 相似文献
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基于NXP公司LPC1100系列处理器设计了一种温度检测网络节点。介绍了网络系统的整个设计方案和温度检测网络节点的硬件设计,并给出功耗管理、温度传感器和ZigBee三个软件模块的具体软件设计方法。 相似文献
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基于LONWORKS网络的多处理器智能节点设计 总被引:7,自引:0,他引:7
在基于LONWORKS网络的现场总线中,Neuron芯片是节点的核心,但是其处理能力不足以胜任复杂的计算任务.为增强节点的计算能力,提出并实现了一种非对称多处理器(AMP)结构的控制节点设计方案,多个处理器之间采用享总线相连,Neuron芯片为主处理器,3个从处理器并行完成信号的高速采样计算.在具体实现中,提出了单缓冲、双通道总线、两级树状网络、通信线程细化等技术手段.按该设计方案实现的总线计轴器 相似文献
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Scalability of a multiprocessor architecture depends on its ability to manage interconnection network latency with increasing number of processors. Interconnection network latency can be minimized by reducing the distance traversed by a message in terms of number of nodes and wire lengths. Scalability of a DSM architecture also depends on the scalability of the coherency protocol and the associated directory storage requirements. In this paper we describe a DSM architecture based on a fat tree interconnection network with augmented switching nodes. The proposed architecture is CC-NUMA, but supports several important features of COMA architectures. The scalability of this architecture is enhanced by integrating routing and cache coherency operations, which helps in improving locality by trapping requests locally. Scalability of a DSM architecture is defined and evaluated in terms of the asymptotic speedup of an algorithm with increasing number of processors. 相似文献
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基于网络处理器的MPLS VPN协议的研究与实现 总被引:1,自引:0,他引:1
MPLS VPN是下一代互联网的主流安全协议之一,本文针对如何在基于网络处理器的高性能路由器中高效实现MPLS VPN协议开展研究.本文在路由器标准功能的软件基础上进行扩 展,提出了基于网络处理器的MPLS VPN协议实现软件结构;利用网络处理器灵活可编程性与高性能的优点,对其关键技术进行了设计与实现;充分发挥了网络处理器在快速协议扩展方面的优势,同时也对网络处理器软件升级的方法进行了有益探索. 相似文献
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Ishfaq Ahmad 《The Journal of supercomputing》1995,9(1-2):135-162
Building large-scale parallel computer systems for time-critical applications is a challenging task since the designers of such systems need to consider a number of related factors such as proper support for fault tolerance, efficient task allocation and reallocation strategies, and scalability. In this paper we propose a massively parallel fault-tolerant architecture using hundreds or thousands of processors for critical applications with timing constraints. The proposed architecture is based on an interconnection network called thebisectional network. A bisectional network is isomorphic to a hypercube in that a binary hypercube network can be easily extended as a bisectional network by adding additional links. These additional links add to the network some rich topological properties such as node symmetry, small diameter, small internode distance, and partitionability. The important property of partitioning is exploited to propose a redundant task allocation and a task redistribution strategy under realtime constraints. The system is partitioned into symmetric regions (spheres) such that each sphere has a central control point. The central points, calledfault control points (FCPs), are distributed throughout the entire system in an optimal fashion and provide two-level task redundancy and efficiently redistribute the loads of failed nodes. FCPs are assigned to the processing nodes such that each node is assigned two types of FCPs for storing two redundant copies of every task present at the node. Similarly, the number of nodes assigned to each FCP is the same. For a failure-repair system environment the performance of the proposed system has been evaluated and compared with a hypercube-based system. Simulation results indicate that the proposed system can yield improved performance in the presence of a high number of node failures. 相似文献
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兰羽 《计算机测量与控制》2021,29(2):262-266
无线传感网络节点功耗直接决定了无线网络的生存周期,为了降低节点能耗,在对多种微处理器芯片和射频芯片性能分析比较的基础上,选择了MSP430F2618处理器芯片和射频芯片CC2520射频芯片,采用微处理器与无线模块独立架构,设计了一种性能灵活无线网络节点;提出了微处理器、射频芯片在工作模式与多种低功耗模式之间切换,以及微处理器时钟的控制等节能策略,在此基础上设计了网络路由节点和端节点软件系统;实验证明:在发射功率为0 dBm,数据传输速率为1 MHz时,设计的节点运行电流和休眠电流(26.1 mA,1.57μA)与传统的Imote节点(35.1 mA,3.6μA)、Mica2节点(56.2 mA,21μA)相比,明显低于传统节点;当节点电池容量为2*700 mAh,工作周期为10分钟时,其生存周期为7.2个月;设计的节点的寿命达到预期目标。 相似文献
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Marco Fillo Stephen W. Keckler William J. Dally Nicholas P. Carter Andrew Chang Yevgeny Gurevich Whay S. Lee 《International journal of parallel programming》1997,25(3):183-212
The M-Machine is an experimental multicomputer being developed to test architectural concepts motivated by the constraints
of modern semiconductor technology and the demands of programming systems. The M-Machine computing nodes are connected with
a 3-D mesh network; each node is a multithreaded processor incorporating 9 function units, on-chip cache, and local memory.
The multiple function units are used to exploit both instruction-level and thread-level parallelism. A user accessible message
passing system yields fast communication and synchronization between nodes. Rapid access to remote memory is provided transparently
to the user with a combination of hardware and software mechanisms. This paper presents the architecture of the M-Machine
and describes how its mechanisms attempt to maximize both single thread performance and overall system throughput. The architecture
is complete and the MAP chip, which will serve as the M-Machine processing node, is currently being implemented. 相似文献
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Byoung Wook Choi Dong Gwan Shin Jeong Ho Park Soo Yeong Yi Seet Gerald 《Intelligent Service Robotics》2009,2(3):139-151
This paper describes the implementation of a dual-kernel software architecture, based on standard Linux and real-time embedded
Linux, for real-time control of service robots in ubiquitous sensor network environments. Mobile robots are used in active
service for the assisted living of elderly people, monitoring their mental and physiological data with wireless sensor nodes.
The data collected from sensor nodes are routed back to a sink node through multi-hop communication. The moving sink node
installed on the main controller of the robot collects data and transmits it to the main controller. To be able to handle
emergency situations, the robot needs to satisfy real-time requirements when processing the data collected, and invoking tasks
to execute. This paper realizes a multi-hop sensor network and proposes real-time software architecture based on Xenomai.
The real-time tasks were implemented, with priority, to rapidly respond to urgent sensor data. In order to validate the deterministic
response of the proposed system, the performance measurements for the delay in handling the sensed data transmission and the
trajectory control with a feedback loop were evaluated on the non real-time standard Linux. 相似文献