Modeling of a constant Voltage transformer

This paper presents a comprehensive nonlinear model of the controlled constant voltage transformer also known as the ferroresonant transformer. Saturation is a normal mode of operation for this device. This paper derives an equivalent electrical circuit that relates to the physical structure of a typical design. The level of detail includes winding resistances, continuously nonlinear magnetizing inductances, tapped windings, and leakage inductances. The paper describes methods to extract the winding resistances, leakage inductances, and hysteresis loops of the transformer and how to fit the latter into single-valued nonlinear functions. The paper compares computer simulation results of the model with those obtained analytically and experimentally. The results show that the derived circuit will be very useful for designers of the ferroresonant transformer, which is used in uninterruptible power supplies.     

Photon-assisted capacitance–voltage study of organic metal–insulator–semiconductor capacitors

The results are reported of a detailed investigation into the photoinduced changes that occur in the capacitance–voltage (C–V) response of an organic metal–insulator–semiconductor (MIS) capacitor based on the organic semiconductor poly(3-hexylthiophene), P3HT. During the forward voltage sweep, the device is driven into deep depletion but stabilizes at a voltage-independent minimum capacitance, C_min, whose value depends on photon energy, light intensity and voltage ramp rate. On reversing the voltage sweep, strong hysteresis is observed owing to a positive shift in the flatband voltage, V_FB, of the device. A theoretical quasi-static model is developed in which it is assumed that electrons photogenerated in the semiconductor depletion region escape geminate recombination following the Onsager model. These electrons then drift to the P3HT/insulator interface where they become deeply trapped thus effecting a positive shift in V_FB. By choosing appropriate values for the only disposable parameter in the model, an excellent fit is obtained to the experimental C_min, from which we extract values for the zero-field quantum yield of photoelectrons in P3HT that are of similar magnitude, 10^?5 to 10^?3, to those previously deduced for π-conjugated polymers from photoconduction measurements. From the observed hysteresis we deduce that the interfacial electron trap density probably exceeds 10¹⁶ m^?2. Evidence is presented suggesting that the ratio of free to trapped electrons at the interface depends on the insulator used for fabricating the device.     

Planar termination for high-voltage p-n junctions

High breakdown voltages are achieved in a planar p-n junction using a deep diffused π ring connected to the main junction. The two-dimensional (2d) Poisson equation is solved and the breakdown voltage is computed with the critical field concept. The effect of several device structure parameters upon the electric field distribution is studied. Lowering the π ring junction depth from 25 to 1 μm significantly lowers the breakdown voltage (from 1850 to 1100 V). Unexpectedly, an optimum Q_ss value is found for a given structure. Experimental results, which confirm the high-voltage capability of this device, are also presented.     

A dc transformer

Although conventional transformers are ac, a device that may be termed a dc transformer has been constructed by using superconductors. To provide an understanding of how such a transformer would operate, some of the properties of type I and type II superconductors are reviewed. Since the dc transformer under discussion is constructed from thin superconducting films, the main emphasis is on these structures; the concept of flux motion is also explained. The result of the work described is a device in which a direct current or voltage can be transformed, and in which it is possible to extract power from the secondary circuit.     

Hole tunneling from valence band and hot-carrier induced hysteresis effect in 0.13 μm partially depleted silicon-on-insulator n-MOSFETs

The hysteresis effect between forward and reverse drain-source voltage (V_DS) sweeps in the transient output characteristics is studied in ultra-thin gate oxide floating-body partially depleted (PD) silicon-on-insulator (SOI) n-MOSFETs. In this study, two mechanisms including direct-tunneling and impact ionization are taken into account. The transient variation of the floating body potential during sweeps leads to the threshold voltage (V_TH) unstable, hence the hysteresis delay occurs. It is proposed that hole tunneling from valence band (HVB) causes positive hysteresis at lower drain-source voltage (V_DS) region, while impact ionization (II) induced floating body charging leads to opposite phenomenon at high V_DS, thus causing threshold voltage unstable in drain bias switching. And our findings reveal that hysteresis effect can be a serious reliability issue in SOI devices with floating body configuration.     

Punch-through currents in P+NP+ and N+PN+ sandwich structures—II: General low-injection theory and measurements

Analytical one-dimensional exponential expressions are derived for the current/voltage characteristics of the punch-through effect in devices where a certain bias voltage is needed to bring the device into punch-through (V_PT > 0) and where punch-through is already present in the non-biased condition (V_PT = 0). Measurements show that the theory can describe the current/voltage relations adequately at low current levels.     

Characteristics of three-terminal metal-tunnel if oxide-n/p+ devices

The device described here comprises a p⁺ substrate containing an epitaxial n-layer, on the surface of which is grown a thin (～50 Å) tunnel oxide. A metal cathode is deposited on the oxide surface, and a metal anode on the back side of the p⁺ substrate. A third terminal, the gate electrode, is connected to the n epilayer to provide for biasing the n-p⁺ junction.The I-V characteristic exhibit two stable states: a high-impedance state and a low-impedance state which are separated by a negative-resistance region. The high-impedance state is stable for applied voltages up to the intrinsic threshold voltage, V_s. When the switching voltage is exceeded, the device switches rapidly to the low-impendance state, which is characterized by a current that increases with little increase in the voltage across the device.The switching voltage may be reduced below V_s by current or voltage biasing of the n-p⁺ junction by means of the gate electrode. Gate efficiencies, the ratio of the change in switching voltage with d.c. gate voltage or current, of 10 V/V and 1.0 V/μA have been observed. Pulsed gate measurements are also presented, and it found that for pulse widths down to 0.1 μs the gate switching characteristics follow the d.c. characteristics. For pulse widths less than 0.1 μs the gate efficiencies are degraded. Suggestions for improving the device characteristics and the turn-on and turn-off time of the device and device reliability are discussed.     

Punch-through impact ionization MOSFET (PIMOS): From device principle to applications

In the present work a punch-through impact ionization MOSFET (PIMOS) is presented, which exploits impact ionization in low-doped body-tied Ω- and tri-gate structures to obtain abrupt switching (3–10 mV/decade) combined with a hysteresis in the I_D(V_DS) and I_D(V_GS) characteristics. The PIMOS device shows an extraordinary temperature stability up to 125 °C. The influence of various parameters on device performance as abrupt switch or memory cell is investigated. Reduction of the electrical channel length, i.e. of gate length and/or substrate doping, reduces the breakdown voltage and hence the DRAM operating voltage, but also increase the I_off. Two architectures for a capacitor-less DRAM cell are demonstrated and evaluated. In addition, a PIMOS n-type hysteretic inverter is demonstrated, which may serve as a 1T SRAM cell.     

Organic memristive devices based on silver nanoparticles and DNA

A novel organic memory device ‘Al/silver nanoparticles-deoxyribonucleic acid-cetyltrimethylammonium Bromide/ITO’ (Al/Ag NPs–DNA–CTMA/ITO) was fabricated. The measured I–V curve of the device exhibits unipolar switching. The conductivity and the memristive characteristics are significantly improved by the introduction of Ag nanoparticles, but with a poor stability. Better stability is achieved by annealing the device, which also changes the switching characteristic from unipolar to bipolar. As the annealing temperature is raised, the switching voltage first decreases and then increases, while the current I_RESET first increases and then decreases. The range of the optimal annealing temperature is from 383 K to 403 K and the maximum ON/OFF current ratio (I_ON/I_OFF) can reach 10⁴. The switching voltage, the current, and I_ON/I_OFF all increase with the applied voltage amplitude, and V_SET and I_ON/I_OFF obey a quadratic and Boltzmann relationship, respectively.     

Efficient and hysteresis-less pseudo-planar heterojunction perovskite solar cells fabricated by a facile and solution-saving one-step dip-coating method

Rough dense sol-gel-derived titanium dioxide (TiO₂) electron-transport layers (ETLs) and smooth organolead halide perovskite (PVK) films for pseudo-planar heterojunction perovskite solar cells (P-PH PVKSCs) were fabricated by a facile one-step dip-coating method. The highly compact TiO₂ ETLs and uniform PVK films endow the device a high power conversion efficiency (PCE) of over 11%, which was nearly identical to that of a reference device (12%) fabricated by conventional spin-coating. Furthermore, the device showed no pronounced hysteresis when tested by scanning the voltage in a forward and backward direction, showing the potential of facile and waste-free dip-coating in replacing of spin-coating for large area perovskite solar cells preparation. Lastly, the hysteresis was compared and discussed and models regarding the abnormal hysteresis, roll-over and current peak phenomena were proposed as well.     

Electrical properties and barrier modification of GaAs MIS Schottky device based on MEH-PPV organic interfacial layer

We report fabrication and electrical characterization of GaAs based metal-interfacial layer-semiconductor (MIS) device with poly[2-methoxy-5-(2^/-ethyl-hexyloxy)-1,4-phenylene vinylene] (MEH-PPV), as an interfacial layer. MEH-PPV raises the barrier height in Al/MEH-PPV/p-GaAs MIS device as high as to 0.87 eV. A Capacitance-Voltage (C–V) characteristic exhibits a low hysteresis voltage with an interface states density of 1.69×10¹¹ cm⁻² eV⁻¹. Moreover, a high transition frequency (f_c) of about 50 kHz was observed in the accumulation mode. The photovoltaic response of Al/MEH-PPV/p-GaAs device was measured under the air masses (AM) 1.0 and 1.5. The open circuit voltage (V_OC), short circuit current (I_SC), fill factor and the efficiency of the Al/MEH-PPV/p-GaAs device were found to be 1.10 V, 0.52 mA, 0.65, and 5.92%, respectively, under AM 1.0 condition.     

A DC current transformer for large bandwidth and high common-moderejection

A review of known magnetic-coupled current-sensing techniques is presented, Subsequently, a novel technique is introduced, based on a configuration discussed in a previous paper. The previous technique made use of a galvanomagnetic device (Hall effect sensor) to sense the magnetization of a current transformer core, so that the sum of the Hall voltage and the voltage across the secondary shunt resistor would yield a faithful copy of the input current. The technique described in this paper makes use of the same principle to obtain a high bandwidth (from DC to 1 MHz) and very high common-mode rejection current transformer, without the need for a Hall effect probe. This is achieved by subtracting the high-frequency components, detected across the secondary shunt resistor, from the voltage across a primary shunt resistor connected in series with the primary of the current transformer. The resulting signal is an accurate image of the transformer magnetizing current, which is then transferred to the secondary side by means of a low-bandwidth isolation amplifier. The high-frequency components are subsequently added, to the amplified and filtered low-frequency components, by means of a third transformer winding, the number of turns of which is chosen to be equal to the gain of the low-frequency amplifier     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Investigations on electrical characteristics and reliability properties of MOS capacitors using HfAlOx on n-GaAs substrates

Radio frequency sputtering system is employed to fabricate metal oxide semiconductor (MOS) capacitors using an ultra-thin layer of HfAlO_x dielectric deposited on n-GaAs substrates with and without a Si interface control layer incorporated in between the dielectric and the semiconductor. Measurements are performed to obtain capacitance voltage (C–V) and current voltage (I–V) characteristics for GaAs/Si/HfAlO_x and GaAs/HfAlO_x capacitors under different constant voltage and constant current stress conditions. The variation of different electrical parameters such as change in interface trap density, hysteresis voltage with various values of constant voltage stress and the dependence of flat band voltage, fractional change in gate leakage current density, etc. with stress time are extracted from the C–V and I–V data for capacitors with and without a Si interlayer. Further the trap charge density and the movement of trap centroid are investigated for various injected influences. The dielectric breakdown and reliability properties of the dielectric films are studied using constant voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd ? 1350 s) is observed for HfAlO_x gate dielectric with a silicon inter-layer under the high constant voltage stress at 8 V. Compared to capacitors without a Si interlayer, MOS capacitors with a Si interlayer exhibit improved electrical and breakdown characteristics, and excellent interface and reliability properties.     

Tailoring Crystal Structure of FA0.83Cs0.17PbI3 Perovskite Through Guanidinium Doping for Enhanced Performance and Tunable Hysteresis of Planar Perovskite Solar Cells

Current–voltage hysteresis of perovskite solar cells (PSCs) has raised the concern of accurate performance measurement in practice. Although various theories have been proposed to elucidate this phenomenon, the origin of hysteresis is still an open question. Herein, the use of guanidinium cation (Gu⁺)‐dopant is demonstrated to tailor the crystal structure of mixed‐cation formamidinium‐cesium lead triiodide (FA_0.83Cs_0.17PbI₃) perovskite, resulting in an improved energy conversion efficiency and tunable current–voltage hysteresis characteristic in planar solar cells. Particularly, when the concentration of Gu‐dopant for the perovskite film increases, the normal hysteresis initially observed in the pristine PSC is first suppressed with 2%‐Gu‐dopant, then changed to inverted hysteresis with a higher Gu‐dopant. The hysteresis tunability behavior is attributed to the interplay of charge/ion accumulation and recombination at interfaces in the PSC. Furthermore, compared to the cell without Gu⁺‐dopant, the optimal content of 2% Gu⁺‐dopant also increases the device efficiency by 14%, reaching over 17% under one sun illumination.     

Fast Resonance Frequency Optical Modulation in Superconducting Stripline Resonator

Fast resonance frequency optical modulation of a superconducting stripline resonator is investigated. The experiments are performed using a novel device which integrates a hot electron detector (HED) into a superconducting stripline ring resonator. Frequency modulation is demonstrated by both applying dc current or voltage to the HED, and by applying optical illumination, with modulation frequencies of up to 4.2 GHz. Potential applications for such a device are in telecommunication, quantum cryptography, and biofluorescence.     

A novel loss-of-signal detector with programmable assert threshold for intelligent limiting amplifier

This paper presents a novel programmable assert threshold loss-of-signal (LOS) detector with fixed optical hysteresis for intelligent limiting amplifier (LA) using 0.5-??m 2P2M CMOS technology. By adjusting the gain of the LA, a programmable threshold range of 2?C20 mV_pp is implemented. The proposed detector circuit obtains a signal strength indication voltage V _SIG and a reference voltage V _REF, both of which can be dependent each other. With other special circuit design techniques, the detector circuit achieves stable LOS range, LOS hysteresis and LOS precision, and all of them are completely independent on all process, voltage supply and temperature deviations. This LOS detector is integrated with a 155-Mbps LA operating at a compatible supply voltage of 3.3 and 5.0?V. The measurement results demonstrate that the LOS detector achieves a stable programmable assert threshold and a 2?dB fixed optical hysteresis for a 155 Mbps input pseudo random sequence.     

Influence of parameters of the semiconductor–dielectric interface on the current of the guard ring of silicon photodiodes

Relationships, which determine requirements for the resistance of the inversion layer for decreasing the influence of the guard ring on the dark current and photodiode noisess and allow obtaining the specified intercoupling coefficient between photosensitive elements in multielement photodiodes, are given. It is shown that dependences of the current of the guard ring on the bias voltage and the charge on the Si–SiO₂ interface in the presence of the inversion layer satisfy the current generation model in the space-charge region of the current. The resistance of the inversion layer increase with an increase in the bias voltage in accordance with the relationship R_u ～ V^1.5.     

On the drain current saturation in short channel MOSFETs

Submicron MOSFETs are the issue for ULSI integrated circuits. However, drastic reduction of device size leads to a complex modeling of the MOSFET drain current, which is affected by the electrical and physical phenomena induced by the low device dimension. Several current models are proposed to explain the drain current behavior in the saturation region of the I_D-V_D characteristic curve. Mainly, we can distinguish two types: long channel and short channel current modeling. In the present work, a survey of current voltage models is presented aiming a contribution to the interpretation of the current behavior in the saturation region of the I-V curves, i.e. non-saturation of the drain current, which are critical in submicronic devices.     

一种低漏感平面变压器

变压器的漏感是电磁干扰的主要来源之一,这是因为开关管在高速关断时,在变压器的漏感上产生感应电动势,叠加在变压器绕组的关断电压上,形成关断电压尖峰,这些电压尖峰不但造成电磁干扰,还会使开关管的电压应力增大,重者可能击穿开关管,并增大开关损耗,降低开关电源的效率。本文提出一种分布磁路结构的低漏感平面变压器,其原边绕组的匝数降低为一匝,副边绕组的等效匝数降低为小于一匝,因而漏感显著减小,这种分布磁路结构可以用于低压大电流电源的变压器,其有效性通过Maxwell 3D得到验证。