Edge current induced failure of semiconductor PN junction during operation in the breakdown region of electrical characteristic

Typical blocking I-V characteristics are shown and analyzed for PN junctions exhibiting a breakdown region above 1000 V from commercial diodes and power MOSFETs. The leakage reverse current of PN junctions from commercial silicon devices available at this time has a flowing component at the semiconductor-passivant material interface around the junction edge.Part of the plotted experimental current-voltage characteristic fits to linear variation and deviation from this variation at higher applied voltage is attributed to non-controlled current flow in the interfacial layer, between the silicon and passivating material from the junction periphery. The thin interfacial layer including atomic layers both from the semiconductor and passivating dielectric material with fixed charges has imperfections resulted from the junction passivation process. For controlled-avalanche PN junctions no deviation from linear voltage dependence of the reverse current is possible until breakdown region practically at right knee appears. For other PN junctions deviation of the reverse current from linear variation results in a breakdown region with round knee and still with visible voltage dependence at current increase. Such soft breakdown region caused by the phenomena in the interfacial layer is exhibited at lower applied reverse voltage than the expected one for breakdown caused by charge carrier avalanche multiplication at the junction. Operation even for short in the soft breakdown region can lead to PN junction failure and for this reason, a maximum working permissible reverse voltage is specified in device data sheet with a value under the breakdown region. Junction failure consists in significantly lower reverse voltage than the initial one or even electrical short-circuit caused by a spot of material degradation in the interfacial layer from the junction periphery. Operation of the controlled-avalanche diode in the breakdown region is possible only for single pulse of short duration and at junction temperature not higher than 175 °C. Above 150-175 °C even for controlled-avalanche diodes deviation from linear variation of the reverse current has been observed and soft breakdown region can appear before the expected avalanche breakdown. Device failure after operation in the breakdown region, caused by spot of material degradation at the junction periphery has occurred in such conditions. For high voltage commercial power MOSFETs operation in the avalanche breakdown region is limited to 150 °C.     

Temperature-dependent I-V characteristics of organic-inorganic heterojunction diodes

In this paper, heterojunctions were fabricated by employing p-type Si and thin films of poly-N-epoxipropylcarbazole (PEPC) doped with tetracyanoquinodimethane (TCNQ). The PEPC films were grown on Si wafers at room temperature but with different gravity (g) conditions:-1, 123, 277, and 1107g. Current-voltage (I-V) characteristics of the grown hybrid structures were evaluated as a function temperature (T) ranging from 20/spl deg/C to 60/spl deg/C. It was found that all samples are p-p isotype heterojunctions and the junctions fabricated at a high value of g, i.e., at 277 and 1107 g, showed reversible rectifying properties as a function of device temperature. Whereas the behavior of devices fabricated at 123 and 1 g were rectifying at room temperature, but became almost nonconductive after treating the samples at 60/spl deg/C. Rectification ratio, threshold voltage, reverse saturation current, and junction resistance of the fabricated junctions were evaluated at different temperatures. At T=60/spl deg/C, the devices grown at 1107 g exhibited rectification ratio less than unity which may be attributed to the switching of the depletion at the interface. This has been explained by assuming the generation of carriers are at elevated temperatures in the organic film, and their subsequent emission from the organic to the inorganic side of the heterojunction.     

Single-electron effect in PtSi/porous Si Schottky junctions

PtSi/porous Si schottky junctions exhibit a breakdown type current-voltage (I-V) curve in reverse bias mode. Below breakdown their current density is much less than regular PtSi/Si junctions. The breakdown voltage decreases with application of infrared radiation for both n and p-type junctions. N-type junctions are sensitive to IR wavelengths of up to 7 /spl mu/m even at room temperature. The small reverse bias current, the change of breakdown voltage with radiation, and IR sensitivity at room temperature can all be explained by single-electron effect. Numerical results show that representative porous schottky junctions exhibit depletion capacitances in 10/sup -19/ f range which is enough to observe single-electron effect at room temperature. Single-electron effect and avalanche multiplication can explain existing experimental data.     

High-power 1320-nm wafer-bonded VCSELs with tunnel junctions

A new long-wavelength vertical-cavity surface-emitting laser structure is described that utilizes AlGaAs-GaAs mirrors bonded to AlInGaAs-InP quantum wells with an intracavity buried tunnel junction. This structure offers complete wavelength flexibility in the 1250-1650 nm fiber communication bands and reduces the high free-carrier losses and bonded junction voltage drops in previous devices. The intracavity contacts electrically bypass the bonded junctions to reduce threshold voltage. N-type current spreading layers and undoped AlGaAs mirrors minimize optical losses. This has enabled 134/spl deg/C maximum continuous-wave lasing temperature, 2-mW room-temperature continuous-wave single-mode power, and 1-mW single-mode power at 80/spl deg/C, in various devices in the 1310-1340 nm wavelength range.     

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.     

Study of reverse dark current in 4H-SiC avalanche photodiodes

Temperature-dependent current-voltage (I-V) measurements have been used to determine the reverse dark current mechanisms in 4H-SiC avalanche photodiodes (APDs). A pn junction vertical mesa structure, passivated with SiO/sub 2/ grown by plasma enhanced chemical vapor deposition, exhibits predominate leakage current along the mesa sidewall. Similar APDs, passivated by thermal oxide, exhibit lower dark current before breakdown; however, when the temperature is higher than 146/spl deg/C, an anomalous dark current, which increases rapidly with temperature, is observed. This current component appears to be eliminated by the removal of the thermal oxide. Near breakdown, tunneling is the dominant dark current mechanism for these pn devices. APDs fabricated from a pp/sup -/n structure show reduced tunneling current. At room temperature, the dark current at 95% of breakdown voltage is 140 fA (1.8 nA/cm/sup 2/) for a 100-/spl mu/m diameter APD. At a gain of 1000, the dark current is 35 pA (0.44 /spl mu/A/cm/sup 2/).     

Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive

A hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb blockade oscillations, along with a high current drive ( /spl sim/ /spl mu/A), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 /spl deg/C to -150 /spl deg/C) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals.     

Some properties of ion-implanted p−n junctions in silicon

Diodes have been made by implantation of boron or gallium ions in n-type, and phosphorus ions in p-type silicon. The doses range from 5 × 10¹² to 10¹⁵ ions/cm², and the energies from 20 to 70 keV. In all diodes the reverse current shows a sharp recovery step upon annealing at 500–600°C. The reverse current after this annealing is typically of the order of 1 nA/cm² at 1 V reverse bias. To overcome the problem of low breakdown voltages usually found for implanted junctions, methods have been developed to enlarge the effective radius of curvature at the edge of the implanted junction. In a planar process with oxide masking, breakdown voltages of 150 V for 3 Ωcm or 1500 V for 300 Ωcm silicon are obtained. This is done by implanting the ions through a tapered oxide, where the oxide walls make an angle of only 3–5° with the silicon surface. The junction depth in this case is 0.4 μm.Another method uses a mask, placed free in front of the slice. Slice and mask rotate during implantation. In this way, a breakdown voltage of 2700 V is obtained with 300 Ωcm silicon.     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.     

Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique

Extremely high breakdown voltages with very low leakage current have been achieved in plane and planar p-n junctions by using an ion-implemented junction extension for precise control of the depletion region charge in the junction termination. A theory is presented which shows a greatly improved control of both the peak surface and bulk electric fields in reverse biased p-n junctions. Experimental results show breakdown voltages greater than 95 percent of the ideal breakdown voltage with lower leakage currents than corresponding unimplanted devices. As an example, diodes with a normal breakdown voltage of 1050 V and a 0.5 mA leakage current become 1400 V (1450 ideal) devices with a 5 µA leakage current. Applications of the junction termination technique is feasible in MOS technology, but is more attractive in power devices where reduced surface fields are as important as the extremely high breakdown voltages. Reduced surface fields allow more flexibility in passivation techniques, two of which we have used to date. Our results also show that the implant can be activated at a variety of temperatures with a good degree of success; process flexibility being the goal of these tests.     

High-voltage planar p-n junctions

A concentric ring junction has been devised to prevent surface breakdown of a planar junction. By properly choosing the spacing between the main junction and the ring, the ring junction acts like a voltage divider at the surface. In addition, the ring junction minimizes the effect of the junction curvature at the periphery of a planar junction. Devices fabricated with three such rings showed breakdown voltages of 2000 and 3200 volts on n-type silicon with impurity concentrations 6.5 × 10¹³and 2.5 × 10¹³cm^-3, respectively. That the structure operated as proposed was corroborated by comparison of the reverse leakage current with a one parameter fit to a theoretically calculated current obtained from the approximated volume of the space charge regions. These results together with the photo response measurements indicate that the field-limiting ring junction can be used successfully to obtain high-voltage planar p-n junctions.     

Forward and reverse current–voltage–temperature characteristics of a typical BPW34 photodiode

The dark forward and reverse current–voltage characteristics of a typical BPW34 silicon photodiode have been investigated in the temperature range 80–300 K. We propose that tunnelling enhanced recombination at or close to the p/i interface plays a significant role in the dark forward current. We show that Bardeen’s model for a modified Schottky-like interfacial junction can be satisfactorily applied to describe the reverse current–voltage characteristics at intermediate bias voltages.     

Low-noise silicon carbide X-ray sensor with wide operating temperature range

A silicon carbide (SiC) sensor is presented with high energy resolution in X-ray spectroscopy over a wide temperature range (27-100/spl deg/C). The sensor, consisting of a Schottky barrier diode on high resistivity epitaxial SiC, is characterised by an extremely low noise due to its ultra-low reverse current density even at high operating temperature (15 pA/cm/sup 2/ at 27/spl deg/C and 0.5 nA/cm/sup 2/ at 100/spl deg/C). Equivalent noise charges as low as 17 electrons rms at 27/spl deg/C and 47 electrons rms at 100/spl deg/C have been measured, allowing X-ray spectroscopy with an energy resolution as low as 315 eV and 797 eV FWHM, respectively.     

High sensitive and wide detecting range MOS tunneling temperature sensors for on-chip temperature detection

This paper examined the feasibility of applying a highly sensitive metal-oxide-semiconductor (MOS) tunneling temperature sensor, which was compatible with current CMOS technology. As the sensor was biased positively at a constant voltage, the gate current increased more than 500 times when the sensor was heated from 20/spl deg/C to 110/spl deg/C. However, when the sensor was biased at a constant-current situation, its gate voltage magnitude changed significantly with substrate temperature, with a sensitivity exceeding -2 V//spl deg/C. The improvement of temperature sensitivity in this paper is one thousand times over the sensitivity of a conventional p-n junction, i.e., namely, about -2 mV//spl deg/C. Regarding a temperature sensor array, this paper proposes a method using gate current gain, rather than absolute gate current, to eliminate the gate current discrepancy among sensors. For constant current operation, a sensitivity exceeding 10 V//spl deg/C can be obtained if the current level is suitable. Finally, this paper demonstrates a real temperature distribution for on-chip detection. With such a high temperature-sensitive sensor, accurate temperature detection can be incorporated into common CMOS circuits.     

Memory characteristics of MOSFETs with densely stacked silicon nanocrystal Layers in the gate oxide synthesized by low-energy ion beam

Densely stacked silicon nanocrystal layers embedded in the gate oxide of MOSFETs are synthesized with Si ion implantation into an SiO/sub 2/ layer at an implantation energy of 2 keV. In this letter, the memory characteristics of MOSFETs with 7-nm tunnel oxide and 20-nm control oxide at various temperatures have been investigated. A threshold voltage window of /spl sim/ 0.5 V is achieved under write/erase (W/E) voltages of +12 V/-12 V for 1 ms. The devices exhibit good endurance up to 10/sup 5/ W/E cycles even at a high operation temperature of 150/spl deg/C. They also have good retention characteristics with an extrapolated ten-year memory window of /spl sim/ 0.3 V at 100/spl deg/C.     

2.5-mW single-mode operation of 1.55-/spl mu/m buried tunnel junction VCSELs

We present 1.55-/spl mu/m wavelength buried tunnel junction InGaAlAs-InP vertical-cavity surface-emitting lasers with low threshold current and high efficiency. An improved mirror design is accomplished with high-reflective low-loss epitaxial InGaAlAs-InAlAs and hybrid dielectric CaF/sub 2/-ZnS-Au layer stacks, respectively. Lasers with aperture diameters of only around 5 /spl mu/m exhibit continuous-wave single-mode output powers at room temperature well beyond 2 mW. Threshold voltages and series resistances as low as 0.9 V and 30-40 /spl Omega/ have been measured. The spectral behavior shows excellent performance over the relevant current and temperature range.     

High efficiency long wavelength VCSEL on InP grown by MOCVD

High efficiency continuous-wave operation of 1.53 /spl mu/m vertical cavity surface emitting lasers (VCSELs) with buried tunnel junction grown by metal organic chemical vapour deposition (MOCVD) has been demonstrated. Devices show a high differential quantum efficiency of 46% and a singlemode power of 1 mW. Minimum threshold current and voltage are 0.45 mA and 1.3 V at room temperature, respectively for devices of 5 /spl mu/m diameter.     

Application of the distributed equilibrium equivalent circuit model to semiconductor junctions

The small-signal equivalent circuits for a p-n junction at equilibrium and the MOS capacitor in the inversion range are derived from the general transmission line model. Detailed calculations are made to obtain the semiconductor admittance as a function of frequency for a gold-doped n-type silicon substrate. The transmission-line model provides the desired distributed time constant observed in experimental data of admittance versus frequency. A simple model is given to illustrate how the low-frequency junction capacitance depends on the position of the deep level recombination center in the band gap and the ratio of the hole and electron emission rates. Experimental results on gold-doped silicon junctions are analyzed in terms of the theoretical model, considering effects of this ratio, the effects of surface channels, and the effect of a nonuniform spatial variation of the gold impurity.     

Frequency dependence of the reverse-biased capacitance of gold-doped silicon P+N step junctions

The experimentally observed frequency dependences of the reverse-biased capacitance of gold-doped silicon step junctions over the frequency range from 10 cps to 30 Mc are found to be in agreement with a simple physical model which takes into account the charge condition and the charging and discharging time constant of the deep-gold acceptor level in the transition region of the junction. Analysis based on the simple physical model provides explicit theoretical formulas for the junction capacitance at low- and high-frequency limits which show that the high-frequency capacitance under reverse bias is approximately proportional tosqrt{N_{D} - N_{Au}}and is considerably reduced below the low frequency or dc capacitance if the donors are nearly compensated by the gold. The frequency effect is important for deep energy level impurities and becomes negligible if the impurity level is at or near the band edges. The presence of gold, however, has negligible effect on the avalanche breakdown voltage ifN_{Au} < N_{D}.     

High-temperature electronics - a role for wide bandgap semiconductors?

The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300/spl deg/C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200/spl deg/C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.