CD4017十进制计数器

整个实验过程包含了集成芯片逻辑功能验证、十进制以内任意计数器的设计、多位计数器的设计等内容。通过面包板实验,学生可以充分理解芯片逻辑功能的验证方法,进而初步掌握应用电路的设计思路,通过设计并搭建电路培养学生的动手实践能力;通过点动触发计数,光敏电阻模块触发计数,声控传感器模块触发计数,自动触发计数,实践计数功能,培养学生理论联系实践的思维方式。     

Wide-Range Precision Speed Measurement with Adaptive Optimization Using a Microcomputer

A new speed measurement method using a microcomputer is presented. In the initial part of the measurement, a definite small fraction of time for one revolution is counted using a software technique. A definite bit-size of the count is maintained by continuing counting over an optimum multiple of the initially measured time interval in case the bit-size of the initial count is less than a preset value. The multiple of the initial time period is measured with the help of an external counter, without any break in the continuity of counting. The speed is computed from the time count and displayed. For this measurement, only a standard digital speed transducer, a counter, and a microcomputer kit are required. The method has a small data acquisition and processing time, and gives a high accuracy that is programmable over a wide range of speed. The method is also quite economical.     

Compact SPAD pixels with fast and accurate photon counting in the analog domain

A compact pixel for single-photon detection in the analog domain is presented.The pixel integrates a single-photon avalanche diode (SPAD),a passive quenching & active recharging circuit (PQARC),and an analog counter for fast and accurate sensing and counting of photons.Fabricated in a standard 0.18μm CMOS technology,the simulated and experimental results reveal that the dead time of the PQARC is about 8 ns and the maximum photon-counting rate can reach 125 Mcps (counting per second).The analog counter can achieve an 8-bit counting range with a voltage step of 6.9 mV.The differential nonlinearity (DNL) and integral nonlinearity (INL) of the analog counter are within the ± 0.6 and ± 1.2 LSB,respectively,indicating high linearity of photon counting.Due to its simple circuit structure and compact layout configuration,the total area occupation of the presented pixel is about 1500μm2,leading to a high fill factor of 9.2％.The presented in-pixel front-end circuit is very suitable for the high-density array integration of SPAD sensors.     

基于同余理论的高速同步计数器设计

本文基于同余理论，建立了模数互质并联同步计数器模型，给出了模数互质并联同步计数器计数值的解析公式．提出了基于中规模同步计数器构建大模数高速同步计数器的方法．实验证明，该方法有效地提高了大模数同步计数器的速度．     

Synchronous decade up/down counter

Sequential up/down counting is required many a time. In this paper, the logical design of such a counter of the parallel carry type is furnished.     

基于NI MULTISIM 11.0软件的数字钟设计与仿真

数字电子钟是一个对标准频率(1Hz)进行计数的计数电路。由振荡电路形成秒脉冲信号,秒脉冲信号输入计数器进行计数,并把累计结果以"时"、"分"、"秒"的数字显示出来。秒计数器电路计满60后触发分计数器电路,分计数器电路计满60后触发时计数器电路,当计满24小时后又开始下一轮的循环计数。由振荡电路、计数器、数码显示器、校时电路、整点报时电路等几部分组成。     

光电编码器输出脉冲的几种计数方法

光电编码器是高精度位置控制系统常用的一种位移检测传感器.在位置控制系统中,由于电机既可能正转,也可能反转,所以要对与其相连的编码器输出的脉冲进行计数,要求相应的计数器既能实现加计数,又能实现减计数,即进行可逆计数.其计数的方法有多种,包括纯粹的软件计数和硬件计数.文中分别对这两种常用的计数方法进行了分析,对其优缺点进行了对比,最后提出了一种新的计数方法,利用8051单片机内部的计数器实现对光电编码器输出脉冲的加减可逆计数,既节省了硬件资源,又能得到较高的计数频率.     

基于STM32点钞机控制系统设计与实现

针对传统点钞机智能化程度低的问题,提出了基于STM32的智能点钞机控制系统设计方法,实现了对多种纸币计数、找零和长期不间断满负荷工作等功能,系统的创新点是设计并实现了简易电机驱动电路实现了电机长期不间断可靠控制,并且提出并通过程序实现了多种纸币鉴别和找零算法,实验结果表明基于STM32点钞机控制系统控制性能稳定、精度高、工作时间长和损耗小等特点.满足了大量多种纸币长期不间断计数工作的要求,有效地提高了纸币清点工作效率.     

微脉冲激光雷达A/D卡同步触发的设计与实现

在微脉冲激光雷达对能见度的测量系统中，常采用光子计数和模／数(A／D)转换两种处理方法进行对比测量，但微脉冲激光器没有Q开关，不能输出与激光脉冲同步的信号，来触发A／D卡采集大气会波信号．本文以高频管和高速单稳触发电路解决了该问题，使整形后的TTL信号的触发沿(上升沿)与激光脉冲的延时相盖50ns，可将测量系统的盲区控制在10m以内．     

A multibit test trigger circuit for megabit SRAMs

A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC pins is especially effective as a 4-Mb SRAM. In addition, the proposed scheme is able to act as a logic trigger for an MBT circuit. The scheme is simple and effective. The logic trigger mode is proposed for future standardization     

Photoelectron Counter Dead Time Effects on Direct Detection Optical Communication Systems

The effects of photon counter dead time on a direct detection binary pulse position modulation optical communication system are computed for both a free space optical channel and an atmospheric channel subject to clear air turbulence. The degradation in the performance of an optimum receiver structure due to dead time losses was found to be typically 1 dB for the free space channel and less than 1 dB for the atmospheric fading channel, even at the large value of the ratio of counter dead time to counting interval length of ten percent.     

74LS161异步置零法构成任意进制计数器的Multisim仿真

介绍了集成4位二进制计数器74LS161异步置零法构成任意进制计数器的Multisim仿真方案,即以波形方式显示计数器的计数过程、过渡状态形成异步置零信号的过程,用四踪示波器以面板部分重叠显示方法同步显示时钟脉冲信号、异步置零信号及状态输出信号。分析了过渡态及异步置零信号的延时方法,指出了Multisim中74LS161计数器时钟触发方式的错误及修正方法。所述方法的创新点是解决了计数器的工作波形无法用电子实验仪器进行分析验证的问题。     

激光尘埃粒子计数器信号幅度概率密度函数

为了研究激光尘埃粒子计数器计数信号幅度概率分布,对激光尘埃粒子计数器计数信号幅度概率分布与传感器光敏区光强分布、采样气流中的粒子数密度、气体层流速度分布之间的关系进行了理论分析。采用自行设计的带保护气套的光电传感器测定粒子计数信号幅度概率分布,给出的分布模型与理论分析相吻合。结果表明,尘埃粒子计数器计数信号幅度概率分布由传感器光敏区光强分布和粒子数密度空间分布共同决定,这为尘埃粒子计数器的设计提供了理论依据。     

正交相位解码器

使用一个简单的状态机调整两个光电池的输出，以控制一个增／减计数器，状态机为计算部件正确提供了滞后作用，而不管方向的变化。     

基于EWB软件的数字钟设计及实现

EWB(Electronics Workbench)是一款方便快捷、功能强大的仿真软件。文章详细介绍了一种利用4518芯片设计数字钟的方法。首次设计出能顺次显示"123456日"的星期计数电路,并用EWB软件进行了仿真,取得了理想的效果。系统主要由振荡器,分频器,计数器,LED显示电路和报时电路组成。最后,本文还介绍了一种具有创新性的星期显示电路。     

数字式超声波测距仪的研制

超声波测距能够实现对物体距离的无接触测量,测距迅速、方便。数字式超声波测距仪由超声波发生电路、超声波接收放大电路、计数和显示电路组成。该数字式超声波测距仪对超声波从发射到返回的时间内输入到计数器特定频率的时钟脉冲进行计数,进而显示对应的测量距离。该测距算法新颖,并给出数字式超声波测距仪各单元电路设计。数字式超声波测距仪,调试简单,制作方便。     

用于超快光计时的时间数字转换器

设计了一款基于延迟锁定环(DLL)和同步计数器结构的10位片上时间数字转换电路(TDC).采用两步层级设计方法,利用同步计数器进行粗量化输出6位二进制码,量化时钟周期的整数倍,再利用高性能差分DLL输出16路固定相移的时钟信号采样,精量化不足一个时钟周期的部分,输出4位温度计码.该结构可以提供较好的精度、动态范围以及转换速度,与传统的子门延时TDC相比,该结构TDC占用的芯片面积更少,转换速度更高,受工艺、电压及温度影响更少.仿真结果表明:该TDC具有LSB 62.5 ps和MSB 64 ns的动态范围,满足一般与时间相关的单光子计数需要.     

尘埃粒子计数器计数损失的分析研究

光散射式尘埃粒子计数器是用来测量空气洁净度的重要仪器，粒子计数器的主要测量误差为重叠损失误差。本文介绍了产生计数损失误差的原因，应用Poisson随机过程分析确定了粒子计数器的计数损失，并提出了测量计数损失的实验方法。最后，给出使用粒子计数器测量中减少计数损失的方法。     

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

This work presents a clock generator with cascaded dynamic frequency counting (DFC) loops for wide multiplication range applications. The DFC loop, which uses variable time period to estimate and tune the frequency of the digitally controlled oscillator (DCO), enhances the resolution of frequency detection. The conventional phase-frequency detector (PFD) and programmable divider are replaced with a digital arithmetic comparator and a DCO timing counter. The value in the DCO timing counter is separated into quotient and remainder vectors. A threshold region is set in the remainder vector to reduce the influence of jitter variation in frequency detection. The loop stability can be retained by cascading two DFC loops when the multiplication factor (N) is large. The proposed clock generator achieves a multiplication range from 4 to 13 888 with output peak-to-peak jitter less than 2.8% of clock period. A test chip for the proposed clock generator is fabricated in 0.18-/spl mu/m CMOS process with core area of 0.16 mm/sup 2/. Power consumption is 15 mW @ 378 MHz with 1.8-V supply voltage.     

激光雷达的单光子计数器计数实现

单光子计数器作为激光雷达的数据采集部件,目的是实现对PMT输出脉冲信号的计数,并把数据实时上传给计算机.鉴于脉冲信号上升时间短、数据量大,本系统选用CPLD作为计数器和控制器,采用门控双通道无缝计数方法,可实现50 ns的门宽分辨率.用一片32 K×16 bit的SRAM做缓存,可满足每50 ns的时间分辨率最大65535次的计数.采用USB作为数据传输接口,可以很好地满足高速、实时的设计要求.