A 110 MHz 350 mW 0.6 μm CMOS 16-state generalized-target Viterbidetector for disk drive read channels

An architecture for efficiently implementing linear and nonlinear Viterbi detectors for magnetic read channels is presented. By employing generalized noiseless target values for the Viterbi trellis, the detector is better able to adapt to the actual binary data storage channel and less equalization is needed, resulting in a significant reduction in the probability of error. An implementation example is presented for the case of a 16-state Viterbi detector having a capability of handling any noiseless target of up to five adjacent nonzero values. In a 0.6 μm (drawn) 3.0 V CMOS process, the design has been implemented with a die area of 9 mm² consuming under 350 mW of power when operated at 110 MHz     

Improving the RF performance of 0.18 μm CMOS with deep n-wellimplantation

The radio-frequency (RF) figures of merit of 0.18 μm complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F _t) and maximum oscillation frequency (F_max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F_t and 25% increase in F_max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications     

A 300 MHz digital double-sideband to single-sideband converter in 1μm CMOS

A 43-tap FIR Hilbert transform digital filter chip is described which implements both a double-sideband (DSB) to single-sideband (SSB) conversion with a decimation-by-2 and the converse operation of a SSB to DSB conversion with an interpolation-by-2. Over 70 dB of image rejection is achieved by the Hilbert transform filter. The 3.57×7.07 mm², 45 000 transistor chip was fabricated in a 1 μm N-well CMOS process and operates at sample rates in excess of 300 MHz     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

1.1 Gbit/s RF-interconnect based on 10 GHz RF-modulation in 0.18μm CMOS

An RF-interconnect transceiver based on the RF-modulation and capacitive coupling for a high speed digital interface is presented. The prototype transceiver is implemented in 0.18 μm CMOS technology. It demonstrates a maximum data rate of 1.1 Gbit/s with a 10 GHz RF-modulation. This RF-interconnect is believed to be instrumental for high-speed link applications in multi-memory and microprocessor interfaces     

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

On-chip characterization of interconnect parameters and time delayin 0.18 μm CMOS technology for ULSI circuit applications

A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 μm CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 μm to the 0.18 μm technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance     

A 150 MHz 0.6 μm BiCMOS superscalar microprocessor

An implementation of the Pentium microprocessor architecture in 0.6 μm BiCMOS technology is described. Power dissipation is reduced and performance is enhanced over the previous generation. Processor features, implementation technology, and circuit techniques are discussed. An internal clock rate of 150 MHz is achieved at 3.7 V and -55°C     

The effect of deterministic spatial variations in retrograde wellimplants on shallow trench isolation for sub-0.18 μm CMOS technology

The high energy retrograde well implants for sub-0.18 microns CMOS are done at a normal or near normal incidence to minimize the shadowing due to the thick photoresist edges. The endstation geometry in a high energy implanter results in an incident angle variation across the wafer, which causes strong spatial variations in the well profile and can negatively impact device performance. We show that the spatial variations can have significant impact on shallow trench isolation (STI), by causing in a deterministic pattern the failure of STI devices on a wafer. These spatial variations are important and need to be taken into consideration for STI design     

A room temperature 0.1 μm CMOS on SOI

An advanced 0.1 μm CMOS technology on SOI is presented. In order to minimize short channel effects, relatively thick nondepleted (0.15 μm) SOI film, highly nonuniform channel doping and source-drain extension-halo were used. Excellent short channel effects (SCE) down to channel lengths below 0.1 μm were obtained. It is shown that undepleted SOI results in better short channel effect when compared to ultrathin depleted SOI. Devices with little short channel effect all the way to below 500 Å effective channel length were obtained. Furthermore, utilization of source-drain extension-halo minimizes the bipolar effect inherent in the floating body. These devices were applied to a variety of circuits: Very high speeds were obtained: Unloaded delay was 20 ps, unloaded NAND (FI=FO=3) was 64 ps, and loaded NAND (FI=FO=3, C_L=0.3 pF) delay was 130 ps at supply of 1.8 V. This technology was applied to a self-resetting 512 K SRAM. Access times of 2.5 ns at 1.5 V and 3.5 ns at 1.0 V were obtained     

基于0.18 μm CMOS工艺的超高速比较器

给出了基于TSMC 0．18μm CMOS工艺的1．8V超高速比较器的设计方案；对比较器速度和失调进行综合，设计了一个1GHz超高速低失调比较器；通过Monte Carlo仿真，验证该比较器的失调电压分布范围为-4．5～4．5mV，并进行了版图设计。该比较器应用于低电压A／D转换器设计中，可达到6位以上的精度。     

18μm CMOS工艺条件下的信号完整性分析

通过模拟分析了0.18μm CMOS工艺条件下的信号完整性问题.在进行串扰延迟和噪声分析中发现了一些规律,这些规律对以后的设计有一定的指导意义.     

0.18μm CMOS, Monolithic MSTP ASIC

I. Introduction Motivated by adopting both telecom and data-com traffic into Synchronous Digital Hierarchy (SDH)[1] transport payloads, we develop the mono-lithic Multi-Service Transport Platform (MSTP)[2] Application Specified Integrated Circuit (ASIC) MSEOSX8-6, which is a highly integrated device capable of mapping 10/100/1000Mbit/s Ethernet[3], 155Mbit/s Resilient Packet Ring (RPR)[4], as well as 2.048Mbit/s E1 traffic into SDH STM-1 payloads. On the line side, the chip s…     

Sub 0.5-V bulk-driven LTA in 0.18 μm CMOS

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 μm CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 μW from a 0.5 V supply and provides 10 μs crossover recovery time for a 1 pF load capacitance.     

A Dual-Antenna Phased-Array UWB Transceiver in 0.18-μm CMOS

A dual-antenna ultra-wideband (UWB) transceiver in 0.18-mum CMOS for mode-1 OFDM applications employs the techniques of antenna diversity and integrated RF selectivity to improve robustness to interferers. Optimal selectivity in receiver and band flatness in transmitter are achieved by on-chip calibration of each band. The packaged device achieves an overall noise figure of 4.7 dB, an IIP3 of -0.8 dBm, a TX P1 dB of 3.1 dBm, and an error vector magnitude (EVM) of -27.2 dB for 480 Mb/s. The transmit output spectrum is fully compliant with FCC mask for UWB without any external bandpass filter     

A Ku-Band Frequency Synthesizer in 0.18-μm CMOS Technology

This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum foundry CMOS process. By employing a modified differential Colpitts voltage controlled oscillator to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15GHz, the proposed synthesizer exhibits a reference sideband power of -50dBc and a phase noise of -104.5dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70mW from a 2-V supply voltage     

A 0.18-μm CMOS 1.25-Gbps Automatic-Gain-Control Amplifier

A 1.25-Gbps automatic-gain-control (AGC) amplifier is presented and it has been fabricated in 0.18-mum CMOS technology. To achieve a constant settling time, this AGC amplifier with the proposed variable gain amplifier (VGA) is presented. The measured VGA has a gain tuning range of 28.5 dB from -10 to 18.5 dB, and its measured group delay is about 12.15 ns. For the bit-error rate of 10^-12, the sensitivity and the overload for this AGC amplifier are 25 and 430 mV, respectively. It achieves input dynamic range of 24.7 dB. The power dissipation is 43.2 mW from a single 1.8-V supply voltage. The chip area is 0.82 mm times 0.56 mm includes I/O pads.     

1.5 μm two-section Fabry-Perot wavelength tunable optical filter

A 1.5 μm two-section Fabry-Perot wavelength tunable optical filter is studied. As opposed to DFB filters, this wavelength tunable optical filter has the advantage that the wavelength tuning range and the transmission bandwidth can be designed independently. This two-section Fabry-Perot filter also controls the transmissivity (gain) and the transmission wavelength independently by current injection and the constant-gain and constant-bandwidth wavelength tuning is achieved. The wavelength tuning range is as wide as 188 GHz (15 Å), the constant-gain is as high as 23 dB and the constant-bandwidth is as narrow as 5 GHz during wavelength tuning. A 25-channel wavelength selection with less than -10 dB crosstalk is expected with this filter     

Scaling of poly-encapsulated LOCOS for 0.35 μm CMOS technology

We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 μm CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's beak punchthrough is shown to fundamentally limit the scalability of LOCOS-based schemes for narrow nitride features. A quantitative comparison of bird's beak punchthrough is made between LOCOS, Poly-Buffer LOCOS (PBL), and PELOX. The PELOX scalability is emphasized by evaluating the impact of the polysilicon-sealed cavity length for narrow nitride features. We present the realization of a 1 μm active/isolation pitch fully meeting the geometry and off-leakage requirements of 0.35 μm CMOS technologies (VDS⩽5 V). This field-implant-free isolation module avoids unnecessary process complexity by successfully integrating scaled PELOX with the split well-drive-in scheme. A highlight of this new approach is that the NMOSFET characteristics are largely width-independent down to 0.3 μm dimensions