DC and RF Characteristics of 0.15 pm Power Metamorphic HEMTs

DC and RF characteristics of 0.15 °m GaAs power metamorphic high electron mobility transistors (MHEMT) have been investigated. The 0.15 °m ° 100 °m MHEMT device shows a drain saturation current of 480 mA/mm, an extrinsic transconductance of 830 mS/mm, and a threshold voltage of ‐0.65 V. Uniformities of the threshold voltage and the maximum extrinsic transconductance across a 4‐inch wafer were 8.3% and 5.1%, respectively. The obtained cut‐off frequency and maximum frequency of oscillation are 141 GHz and 243 GHz, respectively. The 8 ° 50 °m MHEMT device shows 33.2% power‐added efficiency, an 18.1 dB power gain, and a 28.2 mW output power. A very low minimum noise figure of 0.79 dB and an associated gain of 10.56 dB at 26 GHz are obtained for the power MHEMT with an indium content of 53% in the InGaAs channel. This excellent noise characteristic is attributed to the drastic reduction of gate resistance by the T‐shaped gate with a wide head and improved device performance. This power MHEMT technology can be used toward 77 GHz band applications.     

High microwave and ultra-low noise performance of fullyion-implanted GaAs MESFETs with Au/WSiN T-shaped gate

Fully ion-implanted n⁺ self-aligned GaAs MESFETs with high microwave and ultra-low-noise performance have been fabricated. T-shaped gate structures composed of Au/WSiN are employed to reduce gate resistance effectively. A very thin and high-quality channel with high carrier concentration can be formed by adopting the optimum annealing temperature for the channel, and the channel surface suffers almost no damage by using ECR plasma RIE for gate formation. GaAs MESFETs with a gate length as short as 0.35 μm demonstrated a maximum oscillation frequency of 76 GHz. At an operating frequency of 18 GHz, a minimum noise figure of 0.81 dB with an associated gain of 7.7 dB is obtained. A K_f factor of 1.4 estimated by Fukui's noise figure equation, which is comparable to those of AlGaAs/GaAs HEMTs with the same geometry, reveals that the quality of the channel is very high     

VCO phase-noise improvement by gate-finger configuration of 0.13-/spl mu/m CMOS transistors

Using a standard logic process, 0.13-/spl mu/m RF CMOS devices with multifinger gate structure have been fabricated. The flicker noise and minimum noise figure characteristics have been investigated with different gate layout splits, where the device parasitic resistance is the determining factor in this issue. The stripe-shaped gate configuration demonstrates better noise performance, due to the reduction of device gate resistance. In addition, the MOS varactors designed with different gate layouts were used in a 5.2-GHz voltage-controlled oscillator (VCO) design, where the VCO with the stripe-shaped (2 /spl mu/m /spl times/ 36 fingers) gate varactor improved about 6 dB in phase-noise performance at 100-kHz offset frequency than that of square-shaped (8 /spl mu/m /spl times/ 9 fingers) gate varactor.     

AlSb/InAs HEMT's for low-voltage, high-speed applications

The design, fabrication, and characterization of 0.1 μm AlSb/InAs HEMT's are reported. These devices have an In_0.4Al _0.6As/AlSb composite barrier above the InAs channel and a p ⁺ GaSb layer within the AlSb buffer layer. The HEMT's exhibit a transconductance of 600 mS/mm and an f_T of 120 GHz at V_Ds=0.6 V. An intrinsic f_T of 160 GHz is obtained after the gate bonding pad capacitance is removed from an equivalent circuit. The present HEMT's have a noise figure of 1 dB with 14 dB associated gain at 4 GHz and V_Ds=0.4 V. Noise equivalent circuit simulation indicates that this noise figure is primarily limited by gate leakage current and that a noise figure of 0.3 dB at 4 GHz is achievable with expected technological improvements. HEMT's with a 0.5 μm gate length on the same wafer exhibit a transconductance of 1 S/mm and an intrinsic f_TL_g, product of 50 GHz-μm     

Pseudomorphic AlGaAs/InGaAs/GaAs High Electron Mobility Transistors with Super Low Noise Performances of 0.41 dB at 18 GHz

Fully passivated low noise AlGaAs/InGaAs/GaAs pseudomorphic (PM) HEMT with wide head T-shaped gates were fabricated by dose split electron beam lithography (DSL). The dimensions of gate head and footprint were optimized by controlling the splitted pattern size, dose, and spaces of each pattern. We obtained stable T-shaped gate of 0.15 μm gate length with 1.35 μm-wide head. The maximum extrinsic transconductance was 560 mS/mm. The minimum noise figure measured at 18 GHz at V_ds = 2 V and I_ds = 17 mA was 0.41 dB with associated gain of 8.19 dB. At 12 GHz, the minimum noise figure and an associated gain were 0.26 and 10.25 dB, respectively. These noise figures are the lowest values ever reported for GaAs-based HEMTs. These results are attributed to the extremely low gate resistance of wide head T-shaped gate having a ratio of the head to footprint dimensions larger than 9.     

Super low-noise HEMTs with a T-shaped WSix gate

A T-shaped quarter-micron gate structure composed of WSi_x /Ti/Pt/Au has been developed for low-noise AlGaAs/GaAs HEMTs. The gate resistance R_g was reduced to 0.3 Ω for devices with 200 μm-wide gates despite using WSi_x, and the source resistance R_s reached 0.28 Ω mm by minimising the source-gate distance using a self-alignment technique. This HEMT exhibited the lowest reported noise figure of 0.54 dB with an associated gain of 12.1 dB at 12 GHz     

High performance 0.1 μm gate-length p-type SiGe MODFET's andMOS-MODFET's

High performance p-type modulation-doped field-effect transistors (MODFET's) and metal-oxide-semiconductor MODFET (MOS-MODFET) with 0.1 μm gate-length have been fabricated on a high hole mobility SiGe-Si heterojunction grown by ultrahigh vacuum chemical vapor deposition. The MODFET devices exhibited an extrinsic transconductance (g_m) of 142 mS/mm, a unity current gain cut-off frequency (f_T) of 45 GHz and a maximum oscillation frequency (f_MAX) of 81 GHz, 5 nm-thick high quality jet-vapor-deposited (JVD) SiO₂ was utilized as gate dielectric for the MOS-MODFET's. The devices exhibited a lower gate leakage current (1 nA/μm at V_gs=6 V) and a wider gate operating voltage swing in comparison to the MODFET's. However, due to the larger gate-to-channel distance and the existence of a parasitic surface channel, MOS-MODFET's demonstrated a smaller peak g _m of 90 mS/mm, f_T of 38 GHz, and f_max of 64 GHz. The threshold voltage shifted from 0.45 V for MODFET's to 1.33 V for MOS-MODFET's. A minimum noise figure (NF_min) of 1.29 dB and an associated power gain (G_a) of 12.8 dB were measured at 2 GHz for MODFET's, while the MOS-MODFET's exhibited a NF _min of 0.92 dB and a G_a of 12 dB at 2 GHz. These DC, RF, and high frequency noise characteristics make SiGe/Si MODFET's and MOS-MODFET's excellent candidates for wireless communications     

DC and microwave characteristics of sub-0.1-μm gate-lengthplanar-doped pseudomorphic HEMTs

Analytical modeling of these very-short-channel HEMTs (high-electron-mobility transistors) using the charge-control model is given. The calculations performed using this model indicate a very high electron velocity in the device channel (3.2±0.2×10⁷ cm/s) and clearly demonstrate the advantages of the planar-doped devices as compared to the conventional uniformly doped HEMTs. Devices with different air-bridged geometries have been fabricated to study the effect of the gate resistance on the sub-0.1-μm HEMT performance. With reduced gate resistance in the air-bridge-drain device, noise figures as low as 0.7 and 1.9 dB were measured at 18 and 60 GHz, respectively. Maximum available gains as high as 13.0 dB at 60 GHz and 9.2 dB at 92 GHz, corresponding to an f_max of 270 GHz, have also been measured in the device. Using the planar-doped pseudomorphic structure with a high gate aspect-ratio design, a noise figure of less than 2.0 dB at 94 GHz is projected based on expected further reduction in the parasitic gate and source resistances     

Design of Low Power 2.4GHz CMOS Cascode LNA with Reduced Noise Figure for WSN Applications

In this paper, a narrowband cascode Low Noise Amplifier (LNA) with shunt feedback is proposed. A typical inductively degenerated cascode LNA can be treated as a Common Source-Common Gate (CS-CG) two stage LNA. The series interstage inductance is connected between CS-CG stages to increase the power gain. An additional inductance which is connected at the gate of CG stage is used to cancel out the parasitic capacitance of CG stage therefore reduces the noise figure of CG stage. The shunt feedback is used to improve the stability and input impedance matching. This configuration provides better input matching, lower noise figure, low power consumption and good reverse isolation. The proposed LNA exhibits the gain of 13 dB, input return loss of ?11 dB, noise figure of 2.2 dB and good reverse isolation of ?42.8 dB at a frequency of 2.4GHz using TSMC 0.13 μm CMOS technology. It produces gain and noise figure better than conventional cascode LNA. The proposed LNA is biased in moderate inversion region for achieving sufficient gain with low power consumption of 1.5mW at a supply voltage of 1.5V.     

Direct ion-implanted 0.12 μm GaAs MESFET with ft of121 GHz and fmax of 160 GHz

An 0.12 μm gate length direct ion-implanted GaAs MESFET exhibiting excellent DC and microwave characteristics has been developed. By using a shallow implant schedule to form a highly-doped channel and an AsH₃ overpressure annealing system to optimize the shallow dopant profile, the GaAs MESFET performance was further improved. Peak transconductance of 500 mS/mm was obtained at I_ds =380 mA/mm. A noise figure of 0.9 dB with associated gain of 8.9 dB were achieved at 18 GHz. The current gain cutoff frequency f_max of 160 GHz indicates the suitability of this 0.12 μm T-gate device for millimeter-wave IC applications     

Microwave performance of 0.25-µm gate length high electron mobility transistors

The performance of 0.25-µm gate length high electron mobility transistors (HEMT's) is reported. Devices were fabricated on layers grown by MBE. One of the heterostructures had no undoped AlGaAS spacer layer (wafer A), whereas the other had a 40-Å spacer layer (wafer B). The maximum stable gain on both wafers was ∼ 12 dB at 18 GHz. The minimum noise figure measured was 0.60 dB at 8 GHz and 1.3 dB at 18 GHz. Wafer A yielded devices with a unity current gain cutoff frequency ftof 65 GHz whereas wafer B gave an ftof 70 GHz. These results can be attributed primarily to the high quality material, low parasitic resistance, and short gate length.     

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FET's. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FET's for practical use. Fabricated (AlGa)As/ GaAs 2DEG FET's exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FET's.     

94-GHz 0.1-μm T-gate low-noise pseudomorphic InGaAs HEMTs

Fabrication of state-of-the-art W-band 0.1-μm T-gate pseudomorphic (PM) InGaAs high electron mobility transistors (HEMTs) is reported. This device achieved a noise figure of 2.1 dB with an associated gain of 6.3 dB at 93.5 GHz. The device has a maximum gain of 9.6 dB at 94 GHz, which extrapolates to an F_max of 290 GHz. This noise figure is claimed to be the lowest ever reported for HEMTs fabricated on GaAs substrates at this frequency range     

High-performance GaAs MESFETs with advanced LDD structure fordigital, analog, and microwave applications

GaAs MESFETs with advanced LDD structure have been developed by using a single resist-layered dummy gate (SRD) process. The advanced LDD structure suppresses the short channel effects, and reduces source resistance, while maintaining a moderate breakdown voltage. The 0.3-μm enhancement-mode devices exhibit a transconductance of 420 mS/mm, while the breakdown voltage of the depletion-mode device (V_th=-500 mV) is larger than 6 V. The standard deviation of the threshold voltage for 0.3-μm devices is less than 30 mV across a 3-in wafer. The 0.3-μm devices exhibit an average cutoff frequency of 47.2 GHz with a standard deviation of 1.3 GHz across a 3-in wafer. The cutoff frequency of a 0.15-μm device is as high as 72 GHz. D-type flip-flop circuits for digital IC applications and preamplifier for analog IC applications fabricated with 0.3-μm gate length devices operate above 10 Gb/s. In addition, the 0.3-μm devices also show good noise performance with a noise figure of 1.1 dB with associated gain of 6.5 dB at 18 GHz. These results demonstrate that GaAs MESFETs with an advanced LDD structure are quite suitable for digital, analog, microwave, and hybrid IC applications     

0.3 dB minimum noise figure at 2.5 GHz of 0.13 μm Si/Si0.58Ge0.42 n-MODFETs

RF and microwave noise performances of strained Si/Si_0.58 Ge_0.42 n-MODFETs are presented for the first time. The 0.13 μm gate devices have de-embedded f_T=49 GHz, f_max =70 GHz and a record intrinsic g_m=700 mS/mm. A de-embedded minimum noise figure NF_min=0.3 dB with a 41 Ω noise resistance R_n and a 19 dB associated gain G_ass are obtained at 2.5 GHz, while NF_min=2.0 dB with G_ass=10 dB at 18 GHz. The noise parameters measured up to 18 GHz and from 10 to 180 mA/mm with high gain and low power dissipation show the potential of SiGe MODFETs for mobile communications     

The effect of high-K gate dielectrics on deep submicrometer CMOSdevice and circuit performance

The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K_gate) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K_gate for different target subthreshold leakage currents has been identified     

Super-low-noise performance of direct-ion-implanted 0.25-μm-gateGaAs MESFET's

The authors report on advanced ion implantation GaAs MESFET technology using a 0.25-μm `T' gate for super-low-noise microwave and millimeter-wave IC applications. The 0.25×200-μm-gate GaAs MESFETs achieved 0.56-dB noise figure with 13.1-dB associated gain at 50% I_DSS and 0.6 dB noise figure with 16.5-dB associated gain at 100% I_DSS at a measured frequency of 10 GHz. The measured noise figure is comparable to the best noise performance of AlGaAs/GaAs HEMTs and AlGaAs/InGaAs/GaAs pseudomorphic HEMTs     

GaAs f.e.t. mixer operation with high intermediate frequencies

GaAs f.e.t. mixer operation is investigated at 6 GHz when the intermediate frequency is around 1 GHz. A 3 dB improvement in noise figure is measured, compared with 30 MHz i.f. operation. Other characteristics, such as conversion gain and dynamic range, are similar. Broadband operation is also investigated. With 0.5 ?m gate device, on s.s.b. noise figure of 5.6 dB is achieved with a conversion gain of 10 dB.     

MICROX-an all-silicon technology for monolithic microwaveintegrated circuits

An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 Ω-cm) silicon substrates, MICROX NMOS transistors of effective gate length 0.25 μm give a maximum frequency of operation, f_max, of 32 GHz and f_T of 23.6 GHz in large-periphery (4 μm×50 μm) devices with no correction for the parasitic effects of the pads. The measured minimum noise figure is 1.5 dB at 2 GHz with associated gain of 17.5 dB, an improvement over previously reported values for silicon FETs     

A new low-noise FET structure

A novel monolithic FET topology has demonstrated improved minimum noise figure when compared with a conventional pi-gate FET. The structure, referred to as the spider FET, has allowed noise figures to be achieved in monolithic LNA applications that are 0.3 dB lower than in the standard 0.5-μm GaAs MESFET ion-implantation process. The improved spider FET performance is achieved by reducing the gate feed resistance and minimizing the parasitic gate-to-source capacitance in the region of the gate feed. The spider FET shows promise in 0.25-μm MESFET and HEMT (high electron mobility transistor) applications, as well as in power FET applications