适用于高精度∑Δ调制器的低电压时钟发生电路

针对高精度的开关电容电路介绍了一种较为新颖的全数字的时钟发生电路,它是由一串单位延时可控电路延时链级联与门组成的"延时与"电路.与同样用途的时钟发生电路相比,该电路具有下列优点抗时钟抖动、抗干扰能力强,时钟占空比可调节,延时沿输出时钟与原时钟的下降沿(上升沿)不交叠,能随CMOS工艺特征尺寸减小而结构复用等.     

适用于高精度Δ调制器的低电压时钟发生电路

针对高精度的开关电容电路介绍了一种较为新颖的全数字的时钟发生电路,它是由一串单位延时可控电路延时链级联与门组成的“延时与”电路。与同样用途的时钟发生电路相比,该电路具有下列优点:抗时钟抖动、抗干扰能力强,时钟占空比可调节,延时沿输出时钟与原时钟的下降沿(上升沿)不交叠,能随CMOS工艺特征尺寸减小而结构复用等。     

住宅小区路灯线路光时控制器设计

根据城镇住宅小区路灯照明的特点,设计了一种新颖的路灯线路光时控制器.光控电路由CMOS同相缓冲器组成的施密特触发器以及光敏电阻等元件组成,时控电路采用CMOS同相缓冲器组成的电容允电式延时电路.对电路组成、工作原理、参数设计进行了介绍,并通过电路仿真证明了其可行性.该控制器电路简单,实用性强,成本低,使用方便,实际使用效果良好.     

高性能CMOS全加器设计

全加器是数字信号处理器、微处理器中的重要单元,它不仅能完成加法,还能参与减法、乘法、除法等运算,所以,提高全加器性能具有重要意义.本文分析了两种普通全加器,运用布尔代数对全加器和函数、进位函数进行全面处理,提取了和函数、进位函数优化函数式.根据最优化函数式,设计了高性能CMOS管级全加器单元电路.这种CMOS全加器电路与常用CMOS全加器电路相比,电路结构简单、芯片面积小、电路传输延迟时间小、运算速度快.     

一种适用于低功耗LDO的CMOS电流基准设计

提出了一种适用于低功耗LDO的新型CMOS电流基准结构,该电路利用处在饱和区以及亚阈值区MOS管不同的温度特性来达到温度补偿,它采用全CMOS结构,具有电路结构简单,温度特性好,版图面积小的优点。基于CSMC0.5μm模型库对其进行了仿真,所设计电路的静态电流是400nA时,当温度在-20-110℃的范围内变化时,电流大小仅改变了3.17nA,且具有二阶温度补偿。     

基于时间放大技术的时间数字转换器的设计

本文基于时间放大技术设计了一种两步式的时间数字转换器(TDC),可应用于高精度的飞行测量领域。本设计采用SMIC 55 nm CMOS工艺,采用环形延时TDC作为粗量化电路,采用游标式TDC作为细量化电路。游标式TDC的精度受到延时失配限制,导致在设计时难以突破更高精度的要求。时间放大器通过放大粗量化产生的时间余量,并继续进行第二次细量化,降低了细量化电路的设计难度。针对传统时间放大器输入范围有限以及放大精确度不足的弊端,提出一种新的时间放大器结构,具有精确放大宽范围输入时间间隔的能力。仿真结果表明,采用该种时间放大器的TDC可实现的分辨率为3.7 ps,测量范围为80 ns,微分非线性(DNL)为0.73 LSB,积分非线性(INL)为0.95 LSB,该设计能够在高线性度下更好地兼顾TDC的分辨率与测量范围。     

一种新型数字式断电延时继电器

介绍了一种采用CMOS数字电路、数字拨盘开关整定、无辅助电源的断电延时继电器的组成及工作原理。阐述了各主要电路的构成及作用，并给出了电路图。结果表明，该继电器由于采用了二级蓄能技术，使继电器的扩展性非常好，通过少些改动可实现二段断电延时、带滑动触点的断电延时、带瞬时触点或多段断电延时。     

高速低抖动时钟稳定电路设计

基于0.18 μm CMOS Mixed Signal工艺,设计实现了用于高速ADC的低抖动时钟稳定电路.在传统延迟锁相环结构(DLL)时钟电路研究基础上进行改进:设计基于RS锁存器的新型鉴相器,消除传统鉴相器相位误差积累效应;采用连续时间积分器取代电荷泵进行时钟占空比检测,减小由于电荷泵充放电电流不一致而导致的误差....     

CMOS特性及其应用(二)

三、CMOS电路的应用举例CMOS电路具有许多优点:噪声容限高、功耗低、允许电源电压有较宽范围的变化等。且其输入阻抗高,利用较小电容即可获得大的时间常数,其阈值电平温度系数小,在温度-55℃～ 125℃范围内阈值电平变化小于5%V_(DD)(而在同样温度范围LTTL阈值电平变化40%V_(CC)以上),因此可用CMOS电路构     

从电子、家用电器元器件到基本电路(三十)

③CMOS门电路 CMOS电路是在MOS电路的基础上发展起来的一种互补对称场效集成电路。 a.CMOS“非”门电路:图134为CMOS"非”门电路,驱动管T1采用N沟道增强型(NMOS),负载管T2采用     

A global delay model for domino cmos circuits with application to transistor sizing

Domino CMOS circuits have played important roles in the design of high-speed VLSI chips such as 32-bit microprocessors and their family chips. Many researchers have worked on the characterization of the delay time and optimal design of domino CMOS circuits using circuit simulators as the main CAD tools. This paper presents a global analytical delay model for an important class of domino CMOS circuits wherein a multitude of n-channel transistors form a series connection. the new model is shown to predict the delay time from the precharging clock edge to the 0.5 V_DD output level with less than 10% error as compared to that from SPICE simulation over the entire design space. the delay model has been applied efficiently to the design automation of domino CMOS circuits modules.     

Complete delay modeling of sub‐threshold CMOS logic gates for low‐power application

In this paper, the propagation delay of a complementary metal‐oxide semiconductor (CMOS) inverter circuit in sub‐threshold regime has been analyzed thoroughly with respect to variable loads, rise and fall time of input, device dimensions and temperature, without neglecting the significant drain induced barrier lowering (DIBL) and body bias effects. In particular, sub‐threshold slope factor and current strength have been modeled with respect to temperature, which would be efficacious for the analysis of sub‐threshold circuit as temperature plays an important role in propagation delay. Transistor stacking has also been modeled considering variation in threshold voltage, sub‐threshold slope factor and DIBL coefficient owing mainly to fluctuation in doping levels. The CMOS inverter delay model together with transistor stacking model has been incorporated in the analysis of propagation delays of NAND and NOR gates. Extensive simulations have been performed under 45 and 22 nm CMOS technology using simulation program with integrated circuit emphasis (SPICE) to ensure the correctness of the analysis. Simulation shows that this model is applicable for the analysis of digital sub‐threshold circuit in sub‐90 nm technology. Copyright © 2015 John Wiley & Sons, Ltd.     

A.I. Kayssi: Delay modeling of CMOS clock drivers

A delay model for CMOS clock drivers loaded by resistive–capacitive interconnect is derived using dimensional analysis. A model for a purely capacitive load is first developed, then the delay model for a capacitor–resistor–capacitor load is derived and verified. The implementation of the delay function for the clock driver uses a combination of lookup table and analytical functions. The accuracy of the models is shown to be within 5% of detailed circuit simulation of a 0.18-micron CMOS process. A simple formula is also given to help in determining whether the resistance of the interconnect has any significant shielding effect on the clock driver.     

An Ultra Low-Power CMOS Automatic Action Potential Detector

We present a low-power complementary metal–oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18- $mu{rm m}$ chip dissipates 780 nW, and it features a size of 0.07 ${rm mm}^{2}$. So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.      

Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole four-throw circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed.     

A numerical model for the oscillation frequency,the amplitude and the phase‐noise of MOS‐current‐mode‐logic ring oscillators

This paper presents a new model for the frequency of oscillation, the oscillation amplitude and the phase‐noise of ring oscillators consisting of MOS‐current‐mode‐logic delay cells. The numerical model has been validated through circuit simulations of oscillators designed with a typical 130 nm CMOS technology. A design flow based on the proposed model and on circuit simulations is presented and applied to cells with active loads. The choice of the cell parameters that minimize phase‐noise and power consumption is addressed. Copyright © 2009 John Wiley & Sons, Ltd.     

Efficient output waveform evaluation of a CMOS inverter based on short‐circuit current prediction

A novel approach for obtaining the output waveform, the propagation delay and the short‐circuit power dissipation of a CMOS inverter is introduced. The output voltage is calculated by solving the circuit differential equation only for the conducting transistor while the effect of the short‐circuit current is considered as an additional charge, which has to be discharged through the conducting transistor causing a shift to the output waveform. The short‐circuit current as well as the corresponding discharging current are accurately predicted as functions of the required time shift of the output waveform. A program has been developed that implements the proposed method and the results prove that a significant speed improvement can be gained with a minor penalty in accuracy. Copyright © 2002 John Wiley & Sons, Ltd.     

A 5‐GHz energy‐efficient tunable pulse generator for ultra‐wideband applications using a variable attenuator for pulse shaping

A new energy‐efficient tunable pulse generator is presented in this paper using 0.13‐µm CMOS technology for short‐range high‐data‐rate 3.1–10.6 GHz ultra‐wideband applications. A ring oscillator consisting of current‐starved CMOS inverters is quickly switched on and off for the duration of the pulse, and the amplitude envelope is shaped with a variable passive CMOS attenuator. The variable passive attenuator is controlled using an impulse that is created by a low‐power glitch generator (CMOS NOR gate). The glitch generator combines the falling edge of the clock and its delayed inverse, allowing the duration of the impulse to be changed over a wide range (500–900 ps) by varying the delay between the edges. The pulses generated with this technique can provide a sharp frequency roll off with high out‐of‐band rejection to help meet the Federal Communications Commission mask. The entire circuit operates in switched mode with a low average power consumption of less than 3.8 mW at 910 MHz pulse repetition frequency or below 4.2 pJ of energy per pulse. It occupies a total area of 725 × 600 µm² including bonding pads and decoupling capacitors, and the active circuit area is only 360 × 200 µm². Copyright © 2011 John Wiley & Sons, Ltd.