A new analog buffer using P-type poly-Si TFTs for active matrix displays

A new simple analog buffer employing p-type low-temperature poly-Si thin-film transistors (TFTs) are proposed and fabricated for the integrated data driving circuits of AMLCD and AMOLED. The new analog buffer does not use any capacitors to store the threshold voltage of a poly-Si TFT, so that it could reduce the output offset by the subthreshold current of poly-Si TFT. The simulation and experimental result exhibit that the buffer output successfully charges the buffer load (/spl sim/20 pF) to the input value quickly by the boot-strapping. The measured output offset voltages are less than /spl plusmn/70 mV when the input varies from 1 to 10 V.     

CMOS voltage reference based on gate work function differences in poly-Si controlled by conductivity type and impurity concentration

A new CMOS voltage reference circuit consisting of two pairs of transistors is presented. One pair exhibits a threshold voltage difference with a negative temperature coefficient (-0.49 mV//spl deg/C), while the other exhibits a positive temperature coefficient (+0.17 mV//spl deg/C). The circuit was robust to process variations and exhibited excellent temperature independence and stable output voltage. Aside from conductivity type and impurity concentrations of gate electrodes, transistors in the pairs were identical, meaning that the system was robust with respect to process fluctuations. Measurements of the voltage reference circuit without trimming adjustments revealed that it had excellent output voltage reproducibility of within /spl plusmn/2%, low temperature coefficient of less than 80 ppm//spl deg/C, and low current consumption of 0.6 /spl mu/A.     

A realization of a below-1-V operational and 30-MS/s sample-and-hold IC with a 56-dB signal-to-noise ratio by applying the current-based circuit approach

This paper demonstrates the low-voltage and low-power operation of a MOS sample-and-hold circuit while preserving speed and accuracy, aiming at the realization of a pipelined low-voltage and low-power analog-to-digital converter on a system large-scale integrated circuit. It was fabricated by utilizing 0.35-/spl mu/m CMOS technology. The main feature of this circuit is that all the input, signals, and output are in the current form. The circuit consists of simple current mirrors. In order to eliminate the signal-dependent current transfer ratio error, voltages at the drain terminals of mirror transistors are fixed as constant. A source degeneration resistor, which is a transistor in the triode operational region, is connected to a mirror transistor in order to alleviate the influence of the threshold and transconductance parameter variations. Control signals are boosted in voltage and applied to the gate of switch NMOS transistors in the signal path in order to reduce the on-resistance of analog switches. A differential configuration is adopted throughout the entire circuit and effectively cancels switch feedthrough errors. As a result, a 30-MS/s operation with a signal-to-noise ratio (SNR) of 56 dB from a 1-V supply has been achieved, when the input current is /spl plusmn/200 /spl mu/A. The chip even operated down to 0.85 V with a 20-MHz clock. The SNR was measured as 50 dB with an input current of /spl plusmn/100 /spl mu/A.     

Sub-1-V CMOS proportional-to-absolute temperature references

Presents a new all-MOS circuit technique for very-low-voltage proportional-to-absolute temperature (PTAT) references. Optimization of supply scaling below the sum of threshold voltages is based on log companding and implemented by operating the MOSFET in weak inversion. The key design equations for current (/spl mu/A) and voltage (sub-100 mV) references and their standard deviations (around 5%) are derived by analytical analysis. Two sub-1-V sub-5-/spl mu/W integrated PTAT references are presented and exhaustively tested for 1.2- and 0.35-/spl mu/m very large scale integration technologies. Both designs report good agreement between analytical, simulated, and experimental data, exhibiting PSRR(DC)+>60 dB. Hence, the resulting PTAT circuits are suitable for very-low-voltage system-on-a-chip applications in digital CMOS technologies.     

On-panel output buffer with offset compensation technique for data driver in LTPS technology

To overcome the offset voltage (V/sub OS/) of output buffer due to large variation on characteristics of thin-film transistor (TFT) in low-temperature polysilicon (LTPS) technology, a class-B output buffer with offset compensation circuit for the data driver is presented in this paper. This proposed class-B output buffer can operate at 50-kHz operation frequency with a 2-8-V output swing for extended graphic array (XGA) application, and it has been demonstrated in 3-/spl mu/m LTPS technology. Using the offset compensation technique, the V/sub OS/ of output buffer can be controlled within /spl plusmn/100 mV under 2-to-8 V signal operation to achieve a high resolution and quality liquid crystal display (LCD) panel.     

Improved a-Si:H TFT pixel electrode circuits for active-matrixorganic light emitting displays

Two improved four thin-film-transistors (TFTs) pixel electrode circuits based on hydrogenated amorphous silicon (a-Si:H) technology have been designed. Both circuits can provide a constant output current level and can be automatically adjusted for TFT threshold voltage variations. The circuit simulation results indicate that an excellent linearity between the output current and input current can be established. An output current level higher than ~5 μA can be achieved with these circuits. This current level can provide a pixel electrode brightness higher than 1000 cd/m² with the organic light-emitting device (OLED) having an external quantum efficiency of 1%. These pixel electrode circuits can potentially be used for the active-matrix organic light-emitting displays (AM-OLEDs)     

Ridge-width dependence on high-temperature continuous-wave quantum-cascade laser operation

We report continuous-wave (CW) operation of quantum-cascade lasers (/spl lambda/=6 /spl mu/m) up to a temperature of 313 K (40/spl deg/C). The maximum CW optical output powers range from 212 mW at 288 K to 22 mW at 313 K and are achieved with threshold current densities of 2.21 and 3.11 kA/cm/sup 2/, respectively, for a high-reflectivity-coated 12-/spl mu/m-wide and 2-mm-long laser. At room temperature (298 K), the power output is 145 mW at 0.87 A, corresponding to a power conversion efficiency of 1.68%. The maximum CW operating temperature of double-channel ridge waveguide lasers mounted epilayer-up on copper heatsinks is analyzed in terms of the ridge width, which is varied between 12 and 40 /spl mu/m. A clear trend of improved performance is observed as the ridge narrows.     

A complete monolithic 10-b D/A converter

A monolithic 10-b plus sign D/A converter has been developed that incorporates all necessary circuit functions including voltage reference and internally compensated high-speed output op amp in a single 82/spl times/148 mil chip. A unique logic switch and current source configuration achieves 0.05 percent nonlinearity with /spl plusmn/10 V compliance current output option as well as true or complementary binary coding. The design constraints and area requirements for scaling of current source emitter areas are reduced by using a new active current-splitting technique. The circuit features a 1.5 /spl mu/s settling time voltage output and sign-magnitude coding.     

Low-voltage temperature sensor for micro-power harvesters in silicon-on-sapphire CMOS

A low-voltage temperature sensor designed for MEMS power harvesting systems is fabricated. The core of the sensor is a bandgap voltage reference circuit operating with a supply voltage in the range 1-1.5 V. The prototype was fabricated on a conventional 0.5 /spl mu/m silicon-on-sapphire (SOS) process. The sensor design consumes 15 /spl mu/A of current at 1 V. The internal reference voltage is 550 mV. The temperature sensor has a digital square wave output the frequency of which is proportional to temperature. A linear model of the dependency of output frequency with temperature has a conversion factor of 1.6 kHz//spl deg/C. The output is also independent of supply voltage in the range 1-1.5 V. Measured results and targeted applications for the proposed circuit are reported.     

Low threshold high-power room-temperature continuous-wave operation diode laser emitting at 2.26 /spl mu/m

Diode lasers emitting at 2.26 /spl mu/m, based on the InGaAsSb-AlGaAsSb materials system, are reported. These devices exhibit high internal quantum efficiency of 78% and low threshold current density of 184.5 A/cm/sup 2/ for a 2-mm-long cavity. Output power up to 700 mW (/spl ap/550 mW) has been obtained at 280 K (300 K) in continuous-wave operation with 100 /spl mu/m/spl times/1 mm lasers. These devices have been coated with an antireflection on the output facet and are mounted epilayer down on a copper block. The working temperature was maintained by a thermoelectric Peltier cooling element.     

Hydrogenated amorphous silicon thin-film transistor arrays fabricated by digital lithography

A jet-printed digital-lithographic method, in place of conventional photolithography, was used to fabricate 64 /spl times/ 64 pixel (300 /spl mu/m pitch) matrix addressing thin-film transistor (TFT) arrays. The average hydrogenated amorphous silicon TFT device within an array had a threshold voltage of /spl sim/3.5 V, carrier mobility of 0.7 cm/sup 2//V/spl middot/s, subthreshold slope of 0.76 V/decade, and an on/off ratio of 10/sup 8/.     

Design and analysis of separate-absorption-transport-charge-multiplication traveling-wave avalanche photodetectors

This paper proposes a novel type of avalanche photodiode-the separate-absorption-transport-charge-multiplication (SATCM) avalanche photodiode (APD). The novel design of photoabsorption and multiplication layers of APDs can avoid the photoabsorption layer breakdown and hole-transport problems, exhibit low operation voltage, and achieve ultra-high-gain bandwidth product performances. To achieve low excess noise and ultra-high-speed performance in the fiber communication regime (1.3/spl sim/1.55 /spl mu/m), the simulated APD is Si-based with an SiGe-Si superlattice (SL) as the photoabsorption layer and traveling-wave geometric structures. The frequency response is simulated by means of a photo-distributed current model, which includes all the bandwidth-limiting factors, such as the dispersion of microwave propagation loss, velocity mismatch, boundary reflection, and multiplication/transport of photogenerated carriers. By properly choosing the thicknesses of the transport and multiplication layers, microwave propagation effects in the traveling-wave structure can be minimized without increasing the operation voltage significantly. A near 30-Gb/s electrical bandwidth and 10/spl times/ avalanche gain can be achieved simultaneously, even with a long device absorption length (150 /spl mu/m) and low operation voltage (/spl sim/12 V). In addition, the ultrahigh output saturation power bandwidth product of this simulated TWAPD structure can also be expected due to the large photoabsorption volume and superior microwave-guiding structure.     

Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements

This paper presents a scheme for the efficient implementation of a low supply voltage continuous-time high-performance CMOS current mirror with low input and output voltage requirements. This circuit combines a shunt input feedback and a regulated cascode output stage to achieve low input resistance and very high output resistance. It can be used as a high-precision current mirror in analog and mixed signal circuits with a power supply close to a transistor's threshold voltage. The proposed current mirror has been simulated and a bandwidth of 40 MHz has been obtained. An experimental chip prototype has been sent for fabrication and has been experimentally verified, obtaining 0.15-V input-output voltage requirements, 100-/spl Omega/ input resistance, and more than 200-M/spl Omega/ (G/spl Omega/ ideally) output resistance with a 1.2-V supply in a standard CMOS technology.     

A low-Voltage 10-bit CMOS DAC in 0.01-mm/sup 2/ die area

A low-voltage 10-bit digital-to-analog converter (DAC) for static/dc operation is fabricated in a standard 0.18-/spl mu/m CMOS process. The DAC is optimized for large integrated circuit systems where possibly dozens of such DAC would be employed for the purpose of digitally controlled analog circuit calibration. The DAC occupies 110 /spl mu/m/spl times/94 /spl mu/m die area. A segmented R-2R architecture is used for the DAC core in order to maximize matching accuracy for a minimal use of die area. A pseudocommon centroid layout is introduced to overcome the layout restrictions of conventional common centroid techniques. A linear current mirror is proposed in order to achieve linear output current with reduced voltage headroom. The measured differential nonlinearity by integral nonlinearity (DNL/INL) is better than 0.7/0.75 LSB and 0.8/2 LSB for 1.8-V and 1.4-V power supplies, respectively. The DAC remains monotonic (|DNL|<1 LSB) as INL reaches 4 LSB down to 1.3-V operation. The DAC consumes 2.2 mA of current at all supply voltage settings.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Novel self-convergent programming method using source-induced band-to-band hot electron injection

The authors describe a novel self-converging programming method using the source-induced band-to-band hot electron (SIBE) injection. This method features low current, high speed, and good reliability, and automatically converges at the desired threshold voltage state without any conventional verification operations. The programming leakage current of this method is only about 3 /spl mu/A//spl mu/m, and the programming time is as low as 30 /spl mu/s. A threshold voltage model is also proposed and shows good consistency with measured results.     

Short-channel metal-gate TFTs with modified Schottky-barrier source/drain

A thin active layer, a fully silicided source/drain (S/D), a modified Schottky-barrier, a high dielectric constant (high-/spl kappa/) gate dielectric, and a metal gate are integrated to realize high-performance thin-film transistors (TFTs). Devices with 0.1-/spl mu/m gate length were fabricated successfully. Low threshold voltage, low subthreshold swing, high transconductance, low S/D resistance, high on/off current ratio, and negligible threshold voltage rolloff are demonstrated. It is thus suggested for the first time that the short-channel modified Schottky-barrier TFT is a solution to carrier out three-dimension integrated circuits and system-on-panel.     

A precision reference voltage source

With increasing temperature the base-emitter voltage of a transistor with a constant current decreases, while the difference in base-emitter voltages of two identical (integrated) transistors having a constant current ratio increases. From the sum of the two voltages a nearly temperature- independent output voltage is obtained if this sum equals the gap voltage of silicon. A reference voltage source of 10 V based on the principle is described. The reference part of the circuit is an integrated circuit, and thin-film resistors with a small relative temperature coefficient are used. An operational amplifier and a few resistors and capacitors complete the circuit. The source has a parabolic temperature characteristic and the temperature peak can be controlled by resistor adjustment. A change of /spl plusmn/10 K in respect of the peak temperature causes an output voltage change of -250 /spl mu/V, while a change of /spl plusmn/30 K causes a change of -2.2 mV. A long-term stability of 10 ppm/month was measured. The circuit can compete with the best available Zener diode sources, and has the added advantage that practically no selection is necessary.     

CMOS voltage references using lateral bipolar transistors

Two bandgap references are presented which make use of CMOS compatible lateral bipolar transistors. The circuits are designed to be insensitive to the low beta and alpha current gains of these devices. Their accuracy is not degraded by any amplifier offset. The first reference has an intrinsic low output impedance. Experimental results yield an output voltage which is constant within 2 mV, over the commercial temperature range (0 to 70/spl deg/C), when all the circuits of the same batch are trimmed at a single temperature. The load regulation is 3.5 /spl mu/V//spl mu/A, and the power supply rejection ratio (PSRR) at 100 Hz is 60 dB. Measurements on a second reference yield a PSRR of minimum 77 dB at 100 Hz. Temperature behaviour is identical to the first circuit presented. This circuit requires a supply voltage of only 1.7 V.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.