一种基于芯片的成品率分析简化方法

许多fab认为基于芯片（die-based）的方法很难适用于包含多种芯片的版图和？昆合的（mixed）缺陷分布，所以不用这种方法来监测成品率的影响，而代之以缺陷密度度量来监测缺陷随着时间的变化。但是缺陷密度难以被转化为受缺陷限制（defect-limited）的成品率，因为它不提供关于存在缺陷的芯片数或芯片上的缺陷数的信息。     

采用边缘清洗技术控制边缘缺陷提高成品率

约有25%的芯片分布在300mm硅片的周边区域,近来的研究表明硅片周边区域的成品率仅为50%左右。芯片生产商越来越重视硅片边缘缺陷对合格率的影响,并积极的研发清洗方案提高良率。例如，采用边缘清洗技术能够控制边缘缺陷源，进而最大限度地提高成品率。     

IC缺陷轮廓的盒维数及其方向的分布特征

为了进行有效的集成电路（ＩＣ）成品率预报及故障分析，与光刻有关的硅片表面缺陷通常被假定为圆形的或方形的．然而，真实的缺陷的形貌是多种多样的．本文讨论了缺陷轮廓所具有的分形特征．该结果为硅片表面缺陷的精细表征及其计算机模拟作了有益的探索     

IC制造中真实缺陷轮廓的分形特征

为了进行有效的集成电路（ＩＣ）成品率预报及故障分析，与光刻有关的硅片表面缺陷通常被假定为圆形的或方形的．然而，真实的缺陷的形貌是多种多样的．本文讨论了缺陷轮廓所具有的分形特征．该结果为硅片表面缺陷的精细表征及其计算机模拟作了有益的探索     

微波单片集成电路的成品率优化

采用建立管芯等效电路模型、灵敏度分析以及统计勘探法对微波单片集成电路进行成品率优化，并编制了软件，加入到ＧａＡｓＩＣＣＡＤ系统中。应用该软件对Ｘ波段低噪声ＭＭＩＣ、超宽带ＭＭＩＣ放大器进行了设计，成品率有较大的提高，电路性能有所改善。     

集成电路功能成品率模拟与设计方法

本文基于在缺陷空间分布和粒径分布的模型，研究并讨论了计算集成电路（ＩＣ）功能成品率的理论和模拟ＩＣ功能成品率的方法．为了验证所研究方法和模型的正确性，对测试图样和实际ＩＣ的功能成品率进行模拟，并分析了影响功能成品率的几个因素，得到了有益的结果．     

微波单片集成电路的成品率优化

采用建立管芯等效电路模型、灵敏度分析以及统计勘探法对微波单片集成电路进行成品率优化，并编制了软件，加入到ＧａＡｓ ＩＣ ＣＡＤ系统中。应用该软件对Ｘ波段低噪声ＭＭＩＣ、超宽带ＭＭＩＣ放大器进行了设计，成品率有较大的提高，电路性能有所改善。     

MCM市场中裸芯片测试对策

未测试芯片的低成品率或信得过芯片（ＫＧＤ）的测试成本代价导致了ＭＣＭ市场的缓慢发展。ＫＧＤ芯片能满足封装芯片标准，所以，半导体制造者们希望排除影响经济效益的技术障碍，从中寻求出路。本文从他们的角度对该形势作了分析。检测的要求范围包括：参数，功能，最高速度，温度升高和加速老化程序。这些测试可在裸芯片上进行或者最好是在完整片子图层上完成。     

片架片盒的正确使用

在硅片加工过程中，大部分时间硅片是放在花兰及传片盒内的。如果花兰维护不当，会对成品率产生相当大的负作用。不过，大部分半导体厂家对周转硅片用品（花兰、传片盒等）很少引起重视。不恰当的处理会导致：a）加速花兰表面磨损，在硅片表面产生很多颗粒，b）花兰发生畸变，致使硅片装载出错，设备停机时间延长；（c）降低周转硅片用品的使用寿命。本文报道一些习惯作法，并提供一些可使这些问题产生的影响传至最小的建议。如今，一般认为管理部门应采取积极的态度，工作环境必须要求有正确的硅片处理方式。简单地改变一下操作方式——有…     

均匀光栅DFB激光器光电特性研究北大核心CSCD

光栅结构的设计和制作直接决定了分布反馈（DFB）半导体激光器光电特性的优劣。采用传输矩阵法模拟了不同光栅耦合因子下随机相位对均匀光栅DFB芯片特性的影响,获得了芯片的光电参数分布。通过分析耦合因子对芯片光电参数分布的影响,提高了DFB芯片的成品率。设计并制备了基于Al Ga In As材料体系的脊波导DFB激光器,最终使芯片双峰比例仅为7.7%、成品率达到60%。对合格品在-40~105℃下的P-I特性和在-40~85℃下的光谱进行了测试,结果表明芯片性能优良,芯片远场发散角为25°和21°。芯片的小信号频带响应和眼图测试结果表明芯片完全满足2.5 Gbit/s的应用要求。     

Poisson process and integrated circuit yield prediction

Initial integrated circuit yield predictions were overly pessimistic because the assumption that defects were a homogeneous random population led to the logarithm of yield linearly declining with increasing chip area. In reality, the yield vs area curve is concave up, which can be successfully modeled by partitioning the wafer into several Poisson subareas of different defect densities. Previously, this partitioning was done by “eye”. Here an algorithm has been developed to do the partitioning. Good results over a wide range of yields have been obtained. For the particular data presented, the yield curves in the range of interest can be described by a negative binomial distribution, which implies the underlying defect density is governed by the gamma distribution. As previously anticipated, both led to overpredictions of the yield for large chip areas.     

An Empirical Comparison of Spatial Randomness Models for Yield Analysis

Yield analysis is an important activity in the assessment and control of semiconductor fabrication processes. Tests of spatial randomness provide a means of enhancing yield analysis by considering the patterns of good and defective chips on the wafer. These patterns can be related to the likely sources of defects during production. This paper compares two approaches for determining spatial randomness based on join-count statistics. The first assumes that a random distribution of defects can be modeled as a spatially homogenous Bernoulli process (SHBP). The second uses a Markov random field (MRF) as the null distribution. While both methods are shown to have good performance, the MRF outperforms the SHBP on both clustered and random defect data.     

A new defect distribution metrology with a consistent discreteexponential formula and its applications

We have proposed a novel discrete exponential distribution function, which describes a defect count distribution on wafers or chips more accurately, especially in near defect-free conditions. The conventional approach based on a gamma probability density function (g-pdf) is known to fail in expressing the defects of defect-free wafers or chips, because it always gives zero as the pdf value. Since the number of defects is countable (discrete distribution should be used) and analyzed in terms of nondefective chip yield, the g-pdf cannot be used because of its inaccuracy in the near defect-free condition. A discrete exponential pdf is introduced corresponding to the defect count distribution. In addition, a convolution formula of the new pdf is derived statistically which can express realistic defect count distribution with multiple defect sources. It is noted that the popular negative binomial yield formula (NBYF) is directly derived with the convoluted discrete exponential distribution, which interprets the cluster factor given in NBYF as the number of different defect sources predicted. It is experimentally proven that defect count distributions are approximated by this new model within an average error of about 0.01 defects per wafer from film deposition process data     

An Alternative Integrated-Circuit Yield Model

This paper develops a model to predict the number of good integrated circuits (the yield) from a semiconductor wafer processing line. The model is different from other published models and predicts observed outcomes better. Many models tend to predict lower yields than those actually achieved because those models are inherently incapable of predicting the average number of good chips per wafer. The model developed in this paper is based on combinatorial analysis and considers the number of die sites on the wafer and the total number of yield detracting defects on the wafer. In contrast the other models referenced require at least two parameters as input data: the area of one die site or chip and the average defect density. A third parameter, the Cdf of the defect density is often implied by the selection of the model.     

基于像素分布特性的IC晶片视觉检测方法

IC晶片制造过程存在多种致命缺陷,致使芯片失效,导致成品率下降.冗余物缺陷是影响IC晶片成品率下降的重要原因,主要造成电路短路错误.针对冗余物缺陷对版图的影响,提出了一种简单可行的缺陷视觉检测方法,以实现冗余物缺陷的识别及电路失效形式的确定.根据摄取的显微图像的图像特征,利用光线补偿技术及形态滤波方法消除干扰噪声,以提高图像质量,采用投影定理及基于像素分布特性的检测方法,实现电路短路形式或缺陷未导致电路失效的识别.     

Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy

In the optimization of the number of good chips per wafer, yield is obviously one key factor. It plays the major role in the manufacturing phase, as at this time circuit design and chip area cannot be modified. In the design phase, however, chip area as the second factor defining good chips per wafer can still be influenced. If there are no strong relationships between yield and chip area, both can be optimized independently. In some cases, however, there are such strong relationships, and an optimum of yield gain versus area growth has to be found. Maybe the most important example where strong relationships between area and yield have to be considered is the estimation of optimum memory redundancy. In this paper, we will review and discuss relationships between yield and area and present methods for optimization of good chips per wafer, with special focus on the optimization of memory redundancy     

提高晶圆扫描效率的方法研究

从测试晶圆上未划切的手机摄像头芯片引出一个问题:如何快速确定晶圆的有效测试范围,提出了"全片扫描"和"边缘扫描"两种方法,阐述实现原理后,分析各自的优缺点,利用实验数据进行效率对比,发现"边缘扫描"效率更高。     

Extraction of wafer-level defect density distributions to improveyield prediction

Defect density distributions play an important role in process control and yield prediction. To improve yield prediction we present a methodology to extract wafer-level defect density distributions better reflecting such chip-to-chip defect density variations that occur in reality. For that, imaginary wafermaps are generated for a variety of different chip areas to calculate a yield-to-area dependency. Based on these calculations a micro density distribution (MDD) will be determined for each wafer that reflects the degree of defect clustering. The single MDD's per wafer may be summarized to also provide a total defect density distribution per lot or any other sample size. Furthermore, the area needed for defect inspection may be reduced to just a fraction of each wafer which reduces time and costs of data collection and analysis     

A model for radial yield degradation as a function of chip size

Yield data was collected from a total of 928 200-mm silicon wafers which were processed using a 1 μm CMOS technology. Each wafer was patterned with one of four chips varying in area from 17 mm² to 132 mm². Wafers with like chips were binned together into a single grand composite wafer for each of the four chip sizes. The yield was subsequently plotted as a function of radius, and a mathematical expression was empirically fitted to the radial yield plots. The coefficients from each of the fitted expressions were then used to form a generalized expression for radial yield degradation as a function of chip size. The method of normalization, and the algorithm used to generate the radial yield plots are discussed. An explanation of the data is offered based on geometrical considerations. The radial yield dependence is then incorporated into more traditional yield models