Low-power programmable gain CMOS distributed LNA

A design methodology for low power MOS distributed amplifiers (DAs) is presented. The bias point of the MOS devices is optimized so that the DA can be used as a low-noise amplifier (LNA) in broadband applications. A prototype 9-mW LNA with programmable gain was implemented in a 0.18-/spl mu/m CMOS process. The LNA provides a flat gain, S/sub 21/, of 8 /spl plusmn/ 0.6dB from DC to 6.2 GHz, with an input impedance match, S/sub 11/, of -16 dB and an output impedance match, S/sub 22/, of -10 dB over the entire band. The 3-dB bandwidth of the distributed amplifier is 7GHz, the IIP3 is +3 dBm, and the noise figure ranges from 4.2 to 6.2 dB. The gain is programmable from -10 dB to +8 dB while gain flatness and matching are maintained.     

Low-power W-band CPWG InAs/AlSb HEMT low-noise amplifier

We present the development of a low-power W-band low-noise amplifier (LNA) designed in a 200-nm InAs/AlSb high electron mobility transistor (HEMT) technology fabricated on a 50-/spl mu/m GaAs substrate. A single-stage coplanar waveguide with ground (CPWG) LNA is described. The LNA exhibits a noise figure of 2.5 dB and an associated gain of 5.6 dB at 90 GHz while consuming 2.0 mW of total dc power. This is, to the best of our knowledge, the lowest reported noise figure for an InAs/AlSb HEMT LNA at 90 GHz. Biased for maximum gain, the single-stage amplifier presents 6.7-dB gain and an output 1-dB gain compression point (P1dB) of -6.7dBm at 90 GHz. The amplifier provides broad-band gain, greater than 5dB over the entire W-band.     

A low power 2.5-5 GHz low-noise amplifier using 0.5-μm GaAs pHEMT technology

正A two-stage 2.5-5 GHz monolithic low-noise amplifier(LNA) has been fabricated using 0.5-μm enhanced mode AlGaAs/GaAs pHEMT technology.To achieve wide operation bandwidth and low noise figure,the proposed LNA uses a wideband matching network and a negative feedback technique.Measured results from 2.5 to 5 GHz demonstrate a minimum of 2.4-dB noise figure and 17-dB gain.The input and output return loss exceeded -10-dB across the band.The power consumption of this LNA is 33 mW.According to the author's knowledge,this is the lowest power consumption LNA fabricated in 0.5-μm AlGaAs/GaAs pHEMT with the comparable performance.     

A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMICfront-end with a low insertion loss switch

This paper describes the design and experimental results of a 1.8-V single-chip CMOS MMIC front-end for 2.4-GHz band short-range wireless communications, such as Bluetooth and wireless LANs. The IC consists of fundamental RF building circuits-a power amplifier (PA), a low-noise amplifier (LNA), and a transmit/receive-antenna switch (SW), including almost all on-chip matching elements. The IC was fabricated using a 0.18-μm standard bulk CMOS technology which has no extra processing steps to enhance the RF performances. Two new circuit-design techniques are introduced in the IC in order to minimize the insertion loss of the SW and realize a higher gain for the PA and LNA despite the utilization of the standard bulk CMOS technology. The first is the derivation of an optimum gate width of the SW to minimize the insertion loss based on small-signal equivalent circuit analysis. The other is the revelation of the advantages of interdigitated capacitors (IDCs) over conventional polysilicon to polysilicon capacitors and the successful use of the IDCs in the LNA and PA. The IC achieves the following sufficient characteristics for practical wireless terminals at 2.1 GHz and 1.8 V: a 5-dBm transmit power at a -1-dB gain compression, a 19-dB gain, an 18-mA current for the PA, a 1.5-dB insertion loss, more than 24-dB isolation, an 11-dBm power handling capability for the SW, a 7.5-dB gain, a 4.5-dB noise figure, and an 8-mA current for the LNA     

A 1.5-V 2–9.6-GHz Inductorless Low-Noise Amplifier in 0.13-μm CMOS

This paper presents an inductorless low-noise amplifier (LNA) design for an ultra-wideband (UWB) receiver front-end. A current-reuse gain-enhanced noise canceling architecture is proposed, and the properties and limitations of the gain-enhancement stage are discussed. Capacitive peaking is employed to improve the gain flatness and -3-dB bandwidth, at the cost of absolute gain value. The LNA circuit is fabricated in a 0.13-mum triple-well CMOS technology. Measurement result shows that a small-signal gain of 11 dB and a -3-dB bandwidth of 2-9.6 GHz are obtained. Over the -3-dB bandwidth, the input return loss is less than -8.3 dB, and the noise figure is 3.6-4.8 dB. The LNA consumes 19 mW from a low supply voltage of 1.5 V. It is shown that the LNA designed without on-chip inductors achieves comparable performances with inductor-based designs. The silicon area is reduced significantly in the inductorless design, the LNA core occupies only 0.05 mm², which is among the smallest reported designs.     

A power efficient differential 20-GHz low noise amplifier with 5.3-GHz 3-dB bandwidth

A 20-GHz differential two-stage low-noise amplifier (LNA) is demonstrated in a foundry digital 130-nm CMOS technology with 8-metal layers. This LNA has 20-dB voltage gain and /spl sim/5.5-dB noise figure at 20GHz with 24-mW power consumption. The measured IP/sub 1 dB/ and IIP/sub 3/ are -11 dBm and -4dBm. Compared to the previously published bulk CMOS LNAs operating above 20GHz, this LNA has exceptionally low power and current consumption especially considering its differential topology and wide bandwidth.     

A modified architecture used for input matching in CMOS low-noise amplifiers

An architecture used for input matching in CMOS low-noise amplifiers (LNAs) is investigated in this paper. In the proposed architecture, gate and source inductors, which are essential in the traditional source inductive degeneration CMOS LNAs, are either reduced or removed. The architecture is finally verified by a narrow-band LNA and a wide-band LNA operating at 2.4-2.5 and 5.1-5.9 GHz, respectively. The narrow-band LNA has measured power gain of 24-dB, noise figure (NF) of 2.6-2.8 dB, and power consumption of 15 mW. The wide-band LNA provides 22.6-24.6-dB power gain and 2.85-3.5-dB NF while drawing 6 mA current from a 1.5-V voltage supply. Compared with their traditional counterparts, the proposed LNAs consume less chip area and present better gain performance.     

A single-chip GaAs MMIC image-rejection front-end for digitalEuropean cordless telecommunications

An active image-rejection filter is presented in this paper, which applies actively coupled passive resonators. The filter has very low noise and high insertion gain, which may eliminate the use of a low-noise amplifier (LNA) in front-end applications. The GaAs monolithic-microwave integrated-circuit (MMIC) chip area is 3.3 mm² . The filter has 12-dB insertion gain, 45-dB image rejection, 6.2-dB noise figure, and dissipates 4.3 mA from a 3-V supply. An MMIC mixer is also presented. The mixer applies two single-gate MESFETs on a 2.2-mm² GaAs substrate. The mixer has 2.5-dB conversion gain and better than 8-dB single-sideband (SSB) noise figure with a current dissipation of 3.5 mA applying a single 5-V supply. The mixer exhibits very good local oscillator (LO)/RF and LO/IF isolation of better than 30 and 17 dB, respectively, Finally, the entire front-end, including the LNA, image rejection filter, and mixer functions is realized on a 5.7-mm ² GaAs substrate. The front-end has a conversion gain of 15 dB and an image rejection of more than 53 dB with 0-dBm LO power. The SSB noise figure is better than 6.4 dB, The total power dissipation of the front-end is 33 mW. The MMIC's are applicable as a single-block LNA and image-rejection filter, mixer, and single-block front-end in digital European cordless telecommunications. With minor modifications, the MMIC's can be applied in other wireless communication systems working around 2 GHz, e.g., GSM-1800 and GSM-1900     

A 4-mW monolithic CMOS LNA at 5.7GHz with the gate resistance used for input matching

Design and measured results of a fully integrated 5.7-GHz CMOS low-noise amplifier (LNA) is presented. To design this LNA, the parasitic input resistance of a metal-oxide-semiconductor field-effect transistor (MOSFET) is converted to 50/spl Omega/ by a simple L-C network, hence eliminating the need for source degeneration. It is shown, by means of compact expressions, that this matching method enhances the effective transconductance of the LNA by a factor that is inversely proportional to a MOSFET's input resistance. The effect of our proposed method on the noise figure (NF) of the LNA is also discussed. With an 11.45-dB power gain and a 3.4-dB NF at 4mW of dc power, the presented LNA achieves the best overall performance when compared with the most recently published LNAs.     

A GSM LNA using mutual-coupled degeneration

This letter presents a low noise amplifier (LNA) input impedance matching technique using mutual coupled inductors. This scheme not only provides the required input impedance matching but also interstage impedance transformation for the cascoded transistor. The mutual coupled inductors also help to improve the circuit's reverse isolation. A 900-MHz global system for mobile communication LNA using this technique is designed and fabricated using 0.35-/spl mu/m standard complementary metal oxide semiconductor technology. It achieves a 17-dB gain, 3.4-dB noise figure, and -5.1-dBm IIP3. The LNA draws 5.6 mA from a single 2.3-V power supply.     

On the design of unilateral dual-loop feedback low-noise amplifiers with simultaneous noise, impedance, and IIP3 match

This work describes the theory and design of a nonenergetic dual-loop feedback low-noise amplifier (LNA) that provides maximum unilateral gain and simultaneous noise and impedance matching conditions. The dual-loop feedback is implemented in the form of transformer current-feedback and inductive series feedback (emitter degeneration). The current-feedback transformer is also used to neutralize the base-collector capacitance (C/sub bc/), by combining it with a properly dimensioned shunt admittance at the collector output. The result is a single-transistor unilateral-gain amplifier with high isolation and good stability, eliminating the need for a cascode stage and thus enableing the use of a lower dc-supply voltage. For the complete LNA, simple design equations are derived for the unilateralization, noise, and impedance matching requirements. Finally, second-harmonic tuning at the source improves the linearity without compromising the simultaneous noise and impedance match. To verify the presented theory, a 900-MHz hybrid Si BJT LNA has been implemented, which achieves 1.3-dB noise figure, 15-dB gain, -55dB isolation, and +10dBm IIP3 using a conventional double poly transistor, consuming I/sub C/=2.5 mA at V/sub CE/=1.5 V.     

GaAs Monolithic MIC's for Direct Broadcast Satellite Receivers

A 12-GHz low-noise amplifier (LNA), a 1-GHz IF amplifier (IFA), and an 11-GHz dielectric resonator oscillator (DRO) have been developed for DBS home receiver applications by using GaAs monolithic microwave integrated circuit (MMIC) technology. Each MMIC chip contains FET's as active elements and self-biasing source resistors and bypass capacitors for a single power supply operation. It also contairns dc-block and RF-bypass capacitors. The three-stage LNA exhibits a 3.4-dB noise figure and a 19.5-dB gain over 11.7-12.2 GHz. The negative-feedback-type three-stage IFA shows a 3.9-dB noise figure and a 23-dB gain over 0.5-1.5 GHz. The DRO gives 10.mW output power at 10.67 GHz, with a frequency stability of 1.5 MHz over a temperature range from -40-80°C. A direct broadcast satellite (DBS) receiver incorporating these MMIC's exhibits an overafl noise figure of /spl les/ 4.0 dB for frequencies from 11.7-12.2 GHz.     

A 1-V transformer-feedback low-noise amplifier for 5-GHz wireless LAN in 0.18-/spl mu/m CMOS

A low-noise amplifier (LNA) uses low-loss monolithic transformer feedback to neutralize the gate-drain overlap capacitance of a field-effect transistor (FET). A differential implementation in 0.18-/spl mu/m CMOS technology, designed for 5-GHz wireless local-area networks (LANs), achieves a measured power gain of 14.2 dB, noise figure (NF, 50 /spl Omega/) of 0.9 dB, and third-order input intercept point (IIP3) of +0.9 dBm at 5.75 GHz, while consuming 16 mW from a 1-V supply. The feedback design is benchmarked to a 5.75-GHz cascode LNA fabricated in the same technology that realizes 14.1-dB gain, 1.8-dB NF, and IIP3 of +4.2 dBm, while dissipating 21.6 mW at 1.8 V.     

SiGe bipolar transceiver circuits operating at 60 GHz

A low-noise amplifier, direct-conversion quadrature mixer, power amplifier, and voltage-controlled oscillators have been implemented in a 0.12-/spl mu/m, 200-GHz f/sub T/290-GHz f/sub MAX/ SiGe bipolar technology for operation at 60 GHz. At 61.5 GHz, the two-stage LNA achieves 4.5-dB NF, 15-dB gain, consuming 6 mA from 1.8 V. This is the first known demonstration of a silicon LNA at V-band. The downconverter consists of a preamplifier, I/Q double-balanced mixers, a frequency tripler, and a quadrature generator, and is again the first known demonstration of silicon active mixers at V-band. At 60 GHz, the downconverter gain is 18.6 dB and the NF is 13.3 dB, and the circuit consumes 55 mA from 2.7 V, while the output buffers consume an additional 52 mA. The balanced class-AB PA provides 10.8-dB gain, +11.2-dBm 1-dB compression point, 4.3% maximum PAE, and 16-dBm saturated output power. Finally, fully differential Colpitts VCOs have been implemented at 22 and 67 GHz. The 67-GHz VCO has a phase noise better than -98 dBc/Hz at 1-MHz offset, and provides a 3.1% tuning range for 8-mA current consumption from a 3-V supply.     

A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers

A fully integrated differential low-power low-noise amplifier (LNA) for ultrawideband (UWB) systems operating in the 3-5-GHz frequency range is presented. A two-section LC ladder input network is exploited to achieve excellent input match in a wideband fashion and to optimize the noise performance. Prototypes fabricated in a digital 0.13-/spl mu/m complementary metal oxide semiconductor technology show the following performance: 9.5-dB peak power gain, 3.5-dB minimum noise figure, -6-dBm input-referred 1-dB compression point, and -0.8-dBm input-referred third-order intercept point, while drawing 11mA from a 1.5-V supply. The realized LNA is compared with previously reported LNAs tailored for the same frequency range.     

Low-voltage 1.9-GHz front-end receiver in 0.5-μm CMOS technology

This paper describes the design of a 1.9-GHz front-end receiver. The target application of the receiver is the personal communications standard PCS1900. Powered by a 1-V supply, the receiver consists of a low noise amplifier (LNA) and a downconversion mixer. The receiver was fabricated within a 0.5-μm CMOS technology. The LNA features 15 dB of gain and a 1.8-dB noise figure. The mixer exhibits 1.5-dB conversion loss, 12-dB noise figure, and 0 dBm 1 dB-compression point     

A miniature Q-band low noise amplifier using 0.13-/spl mu/m CMOS technology

A miniature Q-band low noise amplifier (LNA) using 0.13-/spl mu/m standard mixed signal/radio frequency complementary metal-oxide-semiconductor (CMOS) technology is presented in this letter. This three-stage common source thin-film microstrip LNA achieves a peak gain of 20dB at 43GHz with a compact chip size of 0.525mm/sup 2/. The 3-dB frequency bandwidth ranges from 34 to 44GHz and the minimum noise figure is 6.3dB at 41GHz. The LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain, highest output IP3, and smallest chip size.     

Post-linearization of cascode CMOS low noise amplifier using folded PMOS IMD sinker

A post-linearization technique for the cascode complementary metal oxide semiconductor (CMOS) low noise amplifier (LNA) is presented. The proposed method uses an additional folded cascode positive-channel metal oxide semiconductor field-effect transistor for sinking the third-order intermodulation distortion (IMD3) current generated by the common source stage, while minimizing the degradation of gain and noise figure. This technique is applied to enhance the linearity of CMOS LNA using 0.18-/spl mu/m technology. The LNA achieved +13.3-dBm IIP3 with 12.8-dB gain, 1.4dB NF at 2GHz consuming 8mA from a 1.8-V supply.     

ESD-Protected Wideband CMOS LNAs Using Modified Resistive Feedback Techniques With Chip-on-Board Packaging

A novel modified resistive feedback structure for designing wideband low-noise amplifiers (LNAs) is proposed and demonstrated in this paper. Techniques including feedback through a source follower, an R–C feedback network, a gate peaking inductor inside the feedback loop, and neutralization capacitors are used. Bond-wire inductors and electrostatic devices (ESDs) are co-designed to improve the chip performance. Two LNAs, LNA1 and LNA2, were fabricated using a TSMC digital 90-nm CMOS technology. Both chips were tested on board using chip-on-board packages with ESD diodes added at the inputs and outputs. LNA1 achieves a 3-dB bandwidth of 9 GHz with 10 dB of power gain and a minimum noise figure (NF) of 4.2 dB. LNA2 achieves a 3-dB bandwidth of 3.2 GHz with 15.5 dB of power gain and a minimum NF of 1.76 dB. The two LNAs have third-order intermodulation intercept points of $-$8 and $-$9 dBm. Their power consumptions are 20 and 25 mW with a 1.2-V supply, respectively.      

An ultra-wideband CMOS low noise amplifier for 3-5-GHz UWB system

An ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that combines a narrowband LNA with a resistive shunt-feedback is proposed. The resistive shunt-feedback provides wideband input matching with small noise figure (NF) degradation by reducing the Q-factor of the narrowband LNA input and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18-/spl mu/m CMOS technology for a 3.1-5-GHz UWB system. Measurements show a -3-dB gain bandwidth of 2-4.6GHz, a minimum NF of 2.3 dB, a power gain of 9.8 dB, better than -9 dB of input matching, and an input IP3 of -7dBm, while consuming only 12.6 mW of power.