用VxWorks的信号量机制实现任务同步

为了保证诸任务对临界critical资源resource的互斥访问,VxWorks提供了任务同步机制.二进制信号量是Vx-Worlsks系统中实现任务同步的一种重要手段,它保证了任务在并发时结果的一致性.简要介绍二进制信号量,阐述用二进制信号量解决任务互斥和同步的方法,并给出二进制信号量应用在某数据采集系统中的程序框架.某数据采集系统中有效地利用了VxWorks的信号量机制,实现了8个接收通道的数据采集、数据存储以及数据查询等任务对缓冲区的共享.     

用VxWorks的信号量机制实现任务同步

为了保证诸任务对临界critical资源resource的互斥访问，VxWorks提供了任务同步机制。二进制信号量是VxWorks系统中实现任务同步的一种重要手段，它保证了任务在并发时结果的一致性。简要介绍二进制信号量，阐述用二进制信号量解决任务互斥和同步的方法，并给出二进制信号量应用在某数据采集系统中的程序框架。某数据采集系统中有效地利用了VxWorks的信号量机制，实现了8个接收通道的数据采集、数据存储以及数据查询等任务对缓冲区的共享。     

Linux内核中信号量机制的研究与实现

信号量是Linux内核中对竞相进入临界区的进程进行同步机制的有效手段。即使在最新版本的Linux-2.6.12内核中,也没有对等待进入临界区的进程链表进行优化,在实时系统中这是一个缺陷,本文重点通过研究内核下的信号量同步机制,针对实时系统提出一种改进的方案。     

一种多文件任务调度算法

计算机在处理多文件任务的时候,会出现同时读写文件的情况,文件将会出现数据读写不全或数据缺失.在Linux内核中,单处理器情况下,通过同步机制来进行任务的分配和处理,其中经典的有原子操作,信号量机制,互斥锁等实现方案.在多处理器系统中则是通过test-and-set原语操作来实现.本文通过设计一种多文件任务调度的算法,避免整个系统发生互斥访问.本文通过Matlab编程实现该算法,其结果表明本文提出的多文件调度算法能够有效的并行执行多文件任务.     

Nucleus PLUS操作系统信号量机制的研究与测试

Nucleus PLUS是一种嵌入式实时操作系统内核.为深入全面地测试其用于任务同步的信号量模块,研究信号量实现机制,尤其是PI信号量中对优先级继承协议的实现,搭建测试环境,编写测试驱动,设计测试用例,开展针对信号量的测试.在常规测试、健壮性测试的基础上,提出基于信号量有限状态机的测试策略.测试效果良好,对操作系统其他内核对象的测试也具有一定的借鉴价值.     

并发程序设计概念和记法(续)

4 基于消息传递的同步原语临界区、管程和路径表达式都是信号量的发展,都是提供控制共享变量访问的结构化方法。另一种不同的发展是消息传递(message passing),它可以看成是把信号量扩充为不仅能进行数据传送而且能实现同步。当使用消息传递进行通信和同步时,进程用发送和接收消息代替对共享变量的读和写。因为进程一收到消息就从发送进程获得了值,因此也达到了通信的目的。因为一个消息只有在被发送后才能被接收,从而控制了这两个事件发生的顺序,也达到了同步的目的。     

带标记信号量——一种新型同步与互斥机制

1 问题的引出信号量机制是E.W.Dijkstra最先提出来的,是并发程序设计中一种基本的、重要的同步与互斥原语,也是研究并发程序行为的重要机制。其描述能力强、机理简单、易于掌握,能方便地描述处理绝大多数并发程序设计的同步与互斥问题(如共享变量的保护)。信号量原语自问世二十余年来,已广泛地应用于     

一种基于发生序和锁集的BPEL数据竞争静态检测方法

BPEL利用flow和link提供了并发和同步的机制,而Isolated Scope则提供了并发情况下对共享变量访问的控制,同时BPEL还引入了死路删除等一些新的特性。对BPEL流程进行了建模,把BPEL流程转化为BCFG图,提出了一种结合发生序和锁集的静态检测BPEL流程数据竞争的方法。该方法利用向量时钟计算BPEL基本块的发生序关系,判断BPEL基本块是否可并发执行,然后根据BPEL基本块是否有锁保护以及对共享变量的访问情况,来判断BPEL流程是否存在数据竞争。锁集的引入提高了数据竞争判断的准确度,另外该方法还引入了对共享变量访问事件冗余度的分析,减少了算法的开销。     

基于任务的SolCS内核实时能力的实现

自主研发一个嵌入式操作系统内核SolCS,其内核主要包括任务管理、中断管理、内存管理、同步与通信管理、时间管理、I/O管理等功能模块。通过对其总体架构的分析与设计,在任务管理方面实现了基于优先级的抢占式任务调度和分时间轮转调度,同时采用信号量机制来实现对临界资源的互斥访问以及利用优先级继承协议来解决优先级逆转的问题,在涉及任务的中断管理方面也作了改进,以此来增强其实时能力,使其可以提高嵌入式应用系统的实时性,能够满足实时应用的要求。     

一种含共享变量维持声明的并行程序语言

现今的并行编程实践多采用锁来同步对共享资源的访问,编程难且易出错;新引入的原子区构造虽简化了编程,但支持其实现的软硬件技术尚不令人满意.本文就同步提出一种新的语言级抽象-共享变量维持声明,它允许程序员从局部于线程的观点声明当前线程对某共享变量s访问的维持需求,即声明当前线程在运行时从上次访问s到这次访问s期间不允许其他线程访问s.从而,程序员无须考虑该如何使用锁等具体机制来同步对共享变量的访问,也可以避免或解决原子区所面临的一些问题.本文给出了共享变量维持声明的语法和语义描述,讨论了由这种声明信息生成共享变量访问控制代码的方法.     

Time-predictable synchronization support with a shared scratchpad memory

Multicore processors need to communicate when working on shared tasks. In classical systems, this is performed via shared objects protected by locks, which are implemented with atomic operations on the main memory. However, access to shared main memory is already a bottleneck for multicore processors. Furthermore, the access time to a shared memory is often hard to predict and therefore problematic for real-time systems.This paper presents a shared on-chip memory that is used for communication and supports atomic operations to implement locks. Access to the shared memory is arbitrated with time division multiplexing, providing time-predictable access. The shared memory supports extended time slots so that a processor can execute more than one memory operation atomically. This allows for the implementation of locking and other synchronization primitives.We evaluate this shared scratchpad memory with synchronization support on a 9-core version of the T-CREST multicore platform. Worst-case access latency to the shared scratchpad is 13 clock cycles. Access to the atomic section under full contention, when every processor core wants access to acquire a lock, is 135 clock cycles.     

基于MS SQL Server 2005 Compact Edition的数据同步机制的研究与实现

移动设备从服务器下载数据,在本地进行数据查询、更改、插入等操作,再与服务器进行数据同步,这是企业应用当中的一种模式.在基于SQL Server 2005 Compact Edition的环境下,可以通过数据库复制及远程数据存取实现.通过对移动设备与数据库服务器同步机制的研究,论述了复制及远程数据存取的编程思想,并通过示例给出程序实现方法.     

Edison: Database-Supported Synchronization for PDAs

One of the most important features provided by personal digital assistants is the ability to synchronize device data with data on a user's PC. Unfortunately, current synchronization protocols have significant shortcomings that limit the availability, usability, and performance of synchronization. We present Edison, a service that leverages existing off-the-shelf ORDBMS technology to address these problems. Edison allows large numbers of users to synchronize handheld devices from any point on the internet with subsets of large, shared data sets. Edison supports this functionality while transferring the minimal amount of data to and from the device. We describe the implementation of the Edison data server and protocol, and show that Edison requires minimal overhead in terms of DBMS storage and additional time per synchronization.     

Decentralized semaphore support in a virtual shared-memory system

Distributed shared memory has increasingly become a desirable programming model on which to program multicomputer systems. Such systems strike a balance between the performance attainable in distributed-memory multiprocessors and the ease of programming on shared-memory systems. In shared-memory systems, concurrent tasks communicate through shared variables, and synchronization of access to shared data is an important issue. Semaphores have been traditionally used to provide this synchronization. In this paper we propose a decentralized scheme to support semaphores in a virtual shared-memory system. Our method of grouping semaphores into semaphore pages and caching a semaphore at a processor on demand eliminates the reliability problems and bottlenecks associated with centralized schemes. We compare the performance of our scheme with a centralized implementation of semaphores and conclude that our system performs better under high semaphore access rates as well as larger numbers of processors.     

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures

High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These “coherence-free” systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both usability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds new challenges in the design of hardware speculative support. In this article, we present a new scheme for hardware transactional memory (HTM) support within a cluster-based, many-core embedded system that lacks an underlying cache-coherence protocol. We propose two alternative data versioning implementations for the HTM support, Full-Mirroring and Distributed Logging and we conduct a performance comparison between them. To the best of our knowledge, these are the first designs for speculative synchronization for this type of architecture. Through a set of benchmark experiments using our simulation platform, we show that our designs can achieve significant performance improvements over traditional lock-based schemes.     

Dataflow Resource Managers and Their Synthesis from Open Path Expressions

The control of concurrent access to shared resources is an important feature of both centralized and distributed operating systems. In conventional systems, exclusive access is the rule while concurrent access is the exception. Dataflow computer systems, along with an applicative style of programming, provide an execution environment in which this philosophy is reversed. In these latter systems, it is necessary to reexamine the manner in which synchronization of access to shared resources is specified and implemented. A basic design for a dataflow resource manager is reviewed, illustrating the clear separation between access mechanism and scheduling policy. The semantics of the access mechanism is based solely on the principle of data dependency. Specifications are presented for a general scheduler to further constrain or order accesses to the resource. Using ``open path expressions' as a very high-level specification language for synchronization, it is shown how to automatically synthesize a scheduler as a distributed network of communicating modules.     

能量限制下基于效用获取的实时节能调度算法

面向基于电池供电的嵌入式实时系统,设计效用获取的实时节能调度算法.在实时系统的研究中,通常采用同步机制来实现任务对资源的互斥共享访问.在这种情况下,调度算法旨在能量受限下获得最大的系统效用,同时满足实时任务的可调度及任务同步.提出了两步节能算法(two-step energyefficient algorithm,TS...     

Reliable synchronization in distributed systems

In distributed computer systems, processors often need to be synchronized to maintain correctness and consistency. Unlike shared-memory parallel systems, the lack of shared memory and a clock considerably complicates the task of synchronization in distributed systems. The objective of this article is two-fold: (1) We present a new randomized agreement algorithm to synchronize cooperating processors in a distributed system. This algorithm achieves the desired agreement in expected five rounds of message exchanges, tolerating a maximum of one-fifth of the processors failures. The algorithm belongs to the class of broadcast-based synchronization problems. (2) We present a new self-stabilization algorithm for an acyclic directed-graph structured distributed systems. This new fault-tolerant algorithm survives all imaginable faults in distributed systems. The algorithm belongs to arbiter-based and broadcast-based synchronization problems.     

Cache-Based Synchronization in Shared Memory Multiprocessors

In shared memory multiprocessors, efficient synchronization is imperative to assure good performance. There are two aspects to the “cost” of a synchronization operation: the first is the waiting time at synchronization points, and the second is the intrinsic overhead in performing the operation. The overhead has two components. The first component deals with contention resolution for synchronization operation among competing processors. The second component deals with the shared data accesses that the processor has to perform once it enters a synchronization region. We present a mechanism to reduce the overhead of performing synchronization operations in a cache-based shared memory multiprocessor. The mechanism is based on the intuitive notion that parallel programs invariably use synchronization operations to govern the access to shared data. Traditional multiprocessor cache protocols treat synchronization accesses the same way as normal read/write memory accesses, leading to inefficiencies in performing synchronization operations which ultimately limit the scalability of such systems. The key idea in our approach is to combine synchronization with the coherence maintenance for the cached data. Each cache line maintains states for synchronization as well as for cache coherence, and the cache protocol ensures the correctness of the synchronization operations and the coherence of the data at these synchronization points. To assess the performance gain due to the proposed mechanism, simulation studies are performed using a workload model that represents a dynamic scheduling paradigm which forms the core of several parallel programs. Results from simulation studies show that the proposed cache-based synchronization performs significantly better than traditional cache coherence approaches.     

High speed synchronization of processors using fuzzy barriers

Parallel programs are commonly written using barriers to synchronize parallel processes. Upon reaching a barrier, a processor must stall until all participating processors reach the barrier. A software implementation of the barrier mechanism using shared variables has two major drawbacks. Firstly, the execution of the barrier may be slow since it requires execution of several instructions. Secondly, processors that are stalled waiting for other processors to reach the barrier cannot do any useful work. In this paper, the notion of thefuzzy barrier is presented, that avoids these drawbacks. The first problem is avoided by implementing the mechanism in hardware. The second problem is solved by extending the barrier concept to include a region of statements that can be executed by a processor while it awaits synchronization. The barrier regions are constructed by a compiler and consist of instructions such that a processor is ready to synchronize upon reaching the first instruction and must synchronize before exiting the region. When synchronization does occur, the processors could be executing at any point in their respective barrier regions. The larger the barrier region, the more likely it is that none of the processors will have to stall. Hardware fuzzy barriers have been implemented as part of a RISC-based multi-processor system. Results based on a software implementation of the fuzzy barrier on the Encore multiprocessor indicate that the synchronization overhead can be greatly reduced using the mechaism.A preliminary version of this paper appeared inASPLOS '89.This work was done while the author was at Philips Laboratories.