Equivalence of multistage interconnection networks

In recent years, many multistage interconnection networks using 2 × 2 switching cells have been proposed for parallel architecture. Here we state a correct and easy graph characterization of all the networks topologically equivalent to the Omega, Flip, Baseline, Reverse Baseline, Indirect Binary Cube, and Modified Data Manipulator networks.     

Alternate resolution strategy in multistage interconnection networks

Multistage interconnection networks have been proposed by many research groups to provide communication between processor and memory module in multiprocessor systems. However, two different processor requests may result in a conflict on the path establishment. For multistage interconnection networks operated in circuit switching mode, the drop approach and the hold approach are often employed to solve the conflict problem in path establishment. In this paper, we propose another resolution, the preemptive hold approach, to solve the conflict problem in path establishment. The proposed approach requires a minor modification in the design of the switching element in multistage interconnection networks. From simulation results, we find that the bandwidth of our proposed resolution approach is higher than those of the other two approaches. Meanwhile, we also propose an analytical model to analyze the bandwidth of the drop approach in multistage interconnection networks.     

若干多级互连网络的扩展Cayley图模型

使用群论中的半直积作为工具,将已有的若干构建互连网络的方法统一成一种Cayley图模型CSC（q,p,l,k）,使其具有更好的可扩展性。并证明了CSC（q,p,l,k）网络包括了若干重要的互连网络作为它的特殊情形,例如立方连通圈、星连通圈和最近提出并受到关注的k度Cayley图。提出该模型的意义在于为计算机系统的设计者们提供只需要选择合适的参数就可以确定自己需要的互连网络模型。其次,该模型也在一定程度上避免一些在互连网络构建方面的冗余研究工作。     

Reliability of a class of multistage interconnection networks

The reliability of extra-stage interconnection networks is discussed. Three types of reliability are analyzed: terminal reliability, which is the probability that at least one fault-free path exists between a given input-output pair: network reliability, which is the probability that at least one fault-free path exists between every input-output pair; and broadcast reliability, which is the probability that at least one fault-free path exists between a given input and all outputs. A recursive expression for the broadcast reliability is obtained. Tight bounds are derived for the network reliability. The numerical results indicate that for practical networks (i.e. when network reliability is at least 0.5) the difference between the upper bound and the lower bound is no more than 2% of the lower bound     

On multistage interconnection networks with small clock cycles

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. Ding and Bhuyan (1994), however, have shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this short note, we present a model for estimating the performance of multibuffered MIN's employing the approach. Using the model, the relative effectiveness of the approach is identified compared to the traditional design     

Fast multicast on multistage interconnection networks using multi-head worms

1IntroductionMulticastcommunication,whichreferstothedeliveryofamessagefromasinglesourcenodetoanumberofdestinationnodes,isfrequentlyusedindistributed-memoryparallelcomputersystemsandnetworks[1].Efficientimplementationofmulticastcommunicationiscriticaltotheperformanceofmessage-basedscalableparallelcomputersandswitch-basedhighspeednetworks.Switch-basednetworksorindirectnetworks,basedonsomevariationsofmultistageiDterconnectionnetworks(MINs),haveemergedasapromisingnetworkajrchitectureforconstruct…     

Simulation of dynamic input buffer space in multistage interconnection networks

This paper presents a simulation study of a new dynamic allocation of input buffer space in multistage interconnection networks (MINs). MINs are composed of an interconnected set of switching elements (SEs), connected in a specific topology. The SEs are composed of input and output buffers which are used to store received and forwarded packets, respectively. The performance of these networks depends on the design of these internal buffers and the clock mechanism in synchronous MINs. Various cycle models exist which include the big cycle, small cycle and the smart cycle, each of which provides a more efficient cycle timing. The smart cycle model achieves a superior performance by using output buffers and acknowledgement. However, it suffers from lost and out-of-order packets at high traffic loads. This paper, presents a variation of the smart cycle model, whereby, the input buffer space of each SE is allocated dynamically as a function of traffic load, in order to overcome the above-mentioned drawbacks. A shared buffer pool is provided, which supplies the required input buffer space as required by each SE. Simulation results are presented, which show the required buffer pool for various network sizes and for different network loads. Also, comparison with a static allocation scheme shows an increased network throughput, and the elimination of lost and out-of-order packets at high traffic loads.     

An introduction to the multistage cube family of interconnection networks

The interconnection network in large-scale parallel/distributed supercomputer systems is a crucial component. Three networks are overviewed here. Multistage cube networks represent an important family of networks, which includes the omega, n-cube, multistage shuffle-exchange, delta, baseline, SW-banyan, and Generalized Cube. This family has been used or proposed for use in such systems as staran, pasm, Ultracomputer, the BBN Butterfly, the IBM RP3, and data-flow machines. The multistage cube topology, distributed routing control, and ability to be partitioned into independent subnetworks are examined. The Extra Stage Cube (ESC), a single-fault-tolerant multistage cube network, is described. The structure, control, and partitionability of the ESC, and how it functions when multiple faults occur, are presented. The Dynamic Redundancy (DR) network, a fault-tolerant multistage cube network that supports the incorporation of spare processors for fault tolerance, is discussed. Its structure, control, and partitionability into single-fault-tolerant subnetworks are explained.This research was supported by the Air Force Office of Scientific Research under grant F49620-86-K-0006, the Rome Air Development Center under grant F30602-83-K-0119, and the Purdue Research Foundation David Ross Grant 1985/86 no. 0857.currently with the Supercomputing Research Center, 4380 Forbes Blvd., Lanham, MD 20706 (as of June 1, 1987).currently with Computer Science Department, University of Illinois, Urbana-Champaign, IL 61801.     

Analyzing permutation capability of multistage interconnection networks with colored Petri nets

In a multistage interconnection network (MIN) the calculation of the number of permutations of the input terminals into the output terminals is a classic difficult problem. In this paper, we introduce an innovative technique based on Colored Petri Nets (known as CP-nets or CPNs) that will allow us to analyze the permutation capability of arbitrary MINs. We show how to verify whether a MIN is rearrangeable through the state space analysis of the associated CP-net and we measure the permutation capability of non-rearrangeable MINs in terms of the permutations that can be generated. The proposed approach takes advantage of powerful existing software tools, particularly, CPNTools, which is used to explore the occurrence graphs of CP-nets and determine the set of permutations performed by the modeled MINs. This new technique is easy to use and can be efficiently applied to MINs made of cross-bar switches.     

Performance analysis of banyan-type multistage interconnection networks under nonuniform traffic pattern

Multistage Interconnection Networks(MINs) have a number of applications in the areas of computer and communications. The most widely researched structure among MIN’s is the (l)banyan type network. It has several variations such as buffered banyan, batcher-banyan, tandem banyan, recirculating banyan and banyan with contention resolution phase. Analytical performance evaluation is crucial for justifying the merit of the design in different operational conditions. While several analytical models have been proposed for the performance evaluation of MINs, they are mainly for uniform traffics. Even the models for nonuniform traffics have several shortcomings such as they only consider output buffered structure or do not consider blocking conditions. In this paper, the more accurate models than any other ones so far have been proposed for the performance evaluation of multibuffered banyan-type MIN’s under nonuniform traffic condition is obtained. The accuracy of proposed models are conformed by comparing with the results from simulation. Firstly, single buffer model is developed. Markov chain is used for the analysis. Multibuffer model is obtained from single buffer model. Simulation is performed using Discrete Evenet Simulaton(DES) method. As a results, proposed model proves to be very accurate.     

A new approach to improve reliability of the multistage interconnection networks

Because of their cost-effectiveness, multistage interconnection networks are widely used in parallel multiprocessor systems to make a connection among the processors and memory modules. One of the most important requirements for these communication systems is reliability. Adding a number of stages to these networks is one of the main approaches to promote this issue. Despite its modest cost and ease of implementation, this approach improves the reliability only to a small extent, which is not desirable, especially for large-scale systems. In this paper, we propose a new approach to improve reliability of the networks, called reducing nodes. Extensive reliability analyses from two major perspectives, terminal and broadcast, demonstrate that this idea can achieve a tremendous advantage over the aforementioned approach.     

Reliable multistage interconnection network design

High-performance supercomputers generally comprise millions of CPUs in which interconnection networks play an important role to achieve high performance. New design paradigms of dynamic on-chip interconnection network involve a) topology b) synthesis, modeling and evaluation c) quality of service, fault tolerance and reliability d) routing procedures. To construct a dynamic highly fault tolerant interconnection networks requires more disjoint paths from each source-destination node pair at each stage and dynamic rerouting capability to use the various available paths effectively. Fast routing and rerouting strategy is needed to provide reliable performance on switch/link failures. This paper proposes two new architecture designs of fault tolerant interconnection networks named as reliable interconnection networks (RIN-1 and RIN-2). The proposed layouts are multipath multi-stage interconnection networks providing four disjoint paths for all the source-destination node pairs with dynamic rerouting capability. The designs can withstand switch failures in all the stages (including input and output stages) and provide more reliability. Reliability analysis of various MIN architectures is evaluated. On comparing the results with some existing MINs it is evident that the proposed designs provides higher reliability values and fault tolerance.     

Fault tolerant permutation mapping in multistage interconnection network

An efficient scheme for fault tolerant mapping of permutations is designed. The proposed algorithm uses extra passes through the network, instead of additional hardware.     

On resource allocation in multistage interconnection network-based systems

A resource allocation problem in a reconfigurable multicomputer architecture based on rectangular banyan multistage interconnection network with arbitrary fanout and arbitrary number of levels is studied. Four commonly used problem structures such as ring, pipeline, broadcast, and macropipeline are introduced and the mapping problem of these structures on the system model, which is equivalent to the resource allocation problem, is discussed. Analytic solutions to several mapping questions are given and generalization of the results to other networks is presented.     

Modelling and performance study of finite-buffered blocking multistage interconnection networks supporting natively 2-class priority routing traffic

In this paper, we model, analyze and evaluate the performance of a 2-class priority architecture for finite-buffered multistage interconnection networks (MINs). The MIN operation modelling is based on a state diagram, which includes the possible MIN states, transitions and conditions under which each transition occurs. Equations expressing state and transition probabilities are subsequently given, providing a formal model for evaluating the MIN's performance. The proposed architecture's performance is subsequently analyzed using simulations; operational parameters, including buffer length, MIN size, offered load and ratios of high priority packets which are varied across experiments to gain insight on how each parameter affects the overall MIN performance. The 2-class priority MIN performance is compared against the performance of single priority MINs, detailing the performance gains and losses for packets of different priorities. Performance is assessed by means of the two most commonly used factors, namely packet throughput and packet delay, while a performance indicator combining both individual factors is introduced, computed and discussed. The findings of this study can be used by network and interconnection system designers in order to deliver efficient systems while minimizing the overall cost. The performance evaluation model can also be applied to other network types, providing the necessary data for network designers to select optimal values for network operation parameters.     

Adaptive routing protocols for hypercube interconnection networks

A taxonomy for characterizing adaptive routing protocols for hypercube interconnection networks (HINs) is presented. The taxonomy is based on classes of routing decisions common to any HIN. This taxonomy is used to discuss existing and proposed protocols. Rather than an exhaustive enumeration of related research, the protocols selected for discussion are intended to be representative of the classes defined by the taxonomy. These protocols are candidates for use in massively parallel architectures configured with HINs. To provide some insight into their behavior in very large HINs, results of simulation studies of representative protocols are presented     

The W-Network: A low-cost fault-tolerant multistage interconnection network for fine-grain multiprocessing

Large-scale multiprocessors require an efficient interconnection network to achieve good performance. This network, like the rest of the system, should be fault-tolerant (able to continue operating even when there are hardware failures). This paper presents the W-Network, a low-cost fault-tolerant MIN which is well-suited to a large multiprocessor running fine-grain parallel programs. It tolerates all single faults without any increases in latency or decreases in band-width following a fault, because it behaves just like the fault-free network even when there is a single fault. It requires only one extra port per chip, which makes it practical for a VLSI implementation. In addition, extra ports can be added for replacing faulty processors with spares.     

Analysis of multiple-bus interconnection networks

The performance of multiple-bus interconnection networks for multiprocessor systems is analyzed, taking into account conflict arising from memory and bus interference. A discrete stochastic model of bandwidth is presented for systems in which each memory is connected either to all the buses or to a subset of the available buses. The effects of the assumptions made concerning independence among requests for different memories (spatial independence) and resubmission of blocked requests (temporal independence) are investigated systematically. The basic bandwidth model is extended to account for spatial dependence, and compared to previously proposed models. Finally, the various analytic models are shown to be in close agreement with simulation results.