Au/p-CdZnTe欧姆接触的研究

研究了在60℃下大气中退火不同时间对Au/p-CdZnTe(CZT)欧姆接触特性的影响.通过I-V测试发现,退火2 h时,Au/p-CZT能得到较好的欧姆接触特性.用SEM和XPS进一步分析发现,在2 h退火过程中,Au大量向CZT体表层扩散,作为受主杂质占据Cd位,对CZT体表层进行了p型重掺杂,形成了M-p -p型欧姆接触.Cd、Te在退火过程中几乎未向Au层扩散,Au在扩散过程中未与CZT中的元素形成任何化合物.同时,CZT侧面有27.01%的Te氧化成有钝化作用的TeO2.     

CdZnTe材料的表面钝化新工艺

研究了一种新的钝化CdZnTe(CZT)器件表面的工艺,即先采用KOH-KCl溶液对CZT表面进行处理,再用NH4F/H2O2溶液对其进行表面氧化的二步法钝化工艺.并借助俄歇电子能谱(AES)、微电流测试仪等手段对其表面钝化层的质量进行了鉴别,同时与KOH-KCl和NH4F/H2O2两种工艺进行了比较.AES能谱分析表明,采用二步法工艺钝化,既可获得化学计量比较好的CZT表面,又可在表面形成一层起保护作用的氧化层.I-Ⅴ特性曲线显示,两步法钝化后CZT器件的漏电流与KOH-KCl和NH4F/H2O2钝化相比都有一定程度的下降.说明文中提出的新工艺在CZT器件制备方面具有良好的应用前景.     

CZT晶体用化学机械抛光液的制备及其性能研究

化学机械抛光工艺是碲锌镉(Cadmium Zinc Telluride,CZT)晶体表面处理的关键技术之一.其中,化学机械抛光液是影响晶片表面质量的重要因素.目前用于CZT晶片的抛光液主要是依靠进口的碱性抛光液,这严重制约了我国CZT晶体研究的发展.采用硅溶胶和次氯酸钠(NaClO)溶液作为主要原料,制备了碱性化学机械抛光液.然后采用该抛光液对CZT晶片表面进行了化学机械抛光,并对抛光表面进行了表征.实验结果表明,抛光后晶片表面的粗糙度小于2 nm,因此采用硅溶胶-次氯酸钠碱性抛光液可制备出高质量的CZT抛光表面.     

CdZnTe材料的表面钝化新工艺

研究了一种新的钝化CdZnTe(CZT)器件表面的工艺，即先采用KOHKCl溶液对CZT表面进行处理，再用NH4F/H2O2溶液对其进行表面氧化的二步法钝化工艺．并借助俄歇电子能谱（AES）、微电流测试仪等手段对其表面钝化层的质量进行了鉴别，同时与KOH KCl和NH4F/H2O2两种工艺进行了比较．AES能谱分析表明，采用二步法工艺钝化，既可获得化学计量比较好的CZT表面，又可在表面形成一层起保护作用的氧化层．I-V特性曲线显示，两步法钝化后CZT器件的漏电流与KOH KCl和NH4F/H2O2钝化相比都有一定程度的下降．说明文中提出的新工艺在CZT器件制备方面具有良好的应用前景．     

碲锌镉晶体化学机械抛光液的研究

本文以硅溶胶为磨料颗粒、次氯酸钠(NaClO)为氧化剂制备适用于CZT晶片的化学机械抛光液.采用XPS能谱分析CZT表面元素化学态,研究CZT化学机械抛光过程中抛光液的化学作用机理,使用激光干涉仪、原子力显微镜研究抛光液中NaClO含量对晶片抛光速率、晶片表面PV值及表面粗糙度Ra的影响.结果表明,硅溶胶-次氯酸钠抛光液通过与CZT晶体中Te单质或CdTe发生化学反应,生成TeO2.随后在一定压力下,抛光盘与CZT晶片发生相对运动,并在硅溶胶磨料颗粒的辅助作用下去除反应物.当NaClO含量在2％～10％时,随着NaClO含量的增加,晶片表面PV值和粗糙度Ra值先降低后升高,去除速率则随着NaClO含量的增加而增加.NaClO含量为6％时,PV值和Ra值最低,得到的晶片表面质量最好.     

中波碲镉汞/钝化层界面电学特性研究

HgCdTe 表面/界面特性对器件性能具有重要的影响,表面/界面的状态主要依赖于表面处理和钝化工艺。采用 Br2/CH3OH 腐蚀液对液相外延（LPE）生长的中波 HgCdTe 薄膜进行表面处理后,使用CdTe/ZnS 复合钝化技术进行表面钝化,制备了相应的 MIS 器件并进行器件 C-V 测试。结果表明,HgCdTe/钝化层界面固定电荷极性为正,面密度为2.1×1011 cm－2,最低快界面态密度为1.43×1011 cm－2·eV－1,在10 V 栅压极值下慢界面态密度为4.75×1011 cm－2,较低的快界面态密度体现出了 CdTe/ZnS 复合钝化技术的优越性。     

不同钝化膜对InSb光伏探测器性能影响研究

采用3种不同钝化膜制备InSb探测器,测试不同周长/面积比二极管芯片的I-V特性曲线,通过对偏置电压为-0.1 V时的暗电流密度进行比较,分析了表面漏电流对InSb探测器性能的影响.实验结果表明SiO2+SiNx复合膜能大幅度降低器件表面暗电流,C-V测试结果也表明复合钝化膜能大幅度降低了界面固定电荷.将复合钝化膜应用到128×12815μm InSb焦平面探测器上,探测器芯片优值因子R0A≥5×104Ω·cm2,较之前(R0A≈5×103Ω·cm2)得到了极大改善.     

开管退火对碲锌镉单晶片沉积相影响的研究

报道了一种CZT单晶片退火的新装置和新工艺,可以方便有效的对CZT单晶片进行开管退火.主要研究了氢气氛下加Cd源开管退火对CZT晶片中沉积相的影响.研究发现:经过开管退火处理后CZT晶片中的沉积相颗粒的密度和尺寸都明显减小,有效消除了Te沉积相,大颗粒的Cd沉积相尺寸也明显减小.     

GaSb晶片表面残留杂质分析

对不同条件下制备的锑化镓抛光晶片表面进行了TOF-SIMS测试比较.结果表明使用体积比为5∶1的HCl与CH3COOH的混合溶液清洗腐蚀(100) GaSb晶片表面,可以有效地去除金属离子、含S离子和大部分有机物,而使用(NH4)2S/(NH4)2SO4混合溶液方法钝化表面,可以使表面大部分Ga和Sb元素硫化,降低了表面态密度.分析比较了清洗和钝化工艺对晶片表面化学成分的影响.     

CdTe钝化膜溅射功率对HgCdTe器件性能的影响研究

采用不同的溅射功率在长波HgCdTe(碲镉汞)薄膜表面沉积了CdTe钝化膜,制备了相应的MIS器件和二极管器件,并对器件进行了I-V测试和C-V测试,研究了溅射功率对CdTe钝化膜和器件性能的影响.结果表明,CdTe钝化膜溅射功率由140 W升高到180 W后,沉积速率显著增加,由3.5 nm/min增加到了9.5 nm/min;HgCdTe/钝化层界面固定电荷面密度增大,由2.43×1011 cm-2增大到了2.83×1011 cm-2;慢界面态密度也随溅射功率的增加而增大.     

Surface passivation of CdZnTe wafers

The chemical polishing process and the subsequent passivation process of CdZnTe wafers were studied. The treatment effects were tested through XPS analysis and I–V measurement. The chemical etching in 2%Br–MeOH solution may effectively remove the damaged layer and improve the ohmic contact between CdZnTe wafer and Au electrodes. CdZnTe wafers after Br–MeOH etching were passivated with five different passivants respectively. It was found that the surface leakage currents of all CdZnTe wafers passivated with different passivants were reduced by 1–2 orders. CdZnTe wafer passivated in NH₄F/H₂O₂ solution showed the best passivation efficiency because the enriched Te on the surface was fully oxidized to TeO₂, which results in the thickest oxide layer, the most stoichiometric surface and the least leakage current. The surface of CdZnTe wafer is Te-rich after passivated in NH₄F/H₂O₂ or H₂O₂ solution and Cd-rich after passivated in KOH or KOH/H₂O₂ solution.     

New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

We propose in this letter a new passivation method to get rid of parasitic surface conduction in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method consists in passivating the HR substrate with a rapid thermal anneal (RTA)-crystallized layer of silicon. The electrical efficiency of this new passivation technique is analyzed and shown to be superior over previously published methods. The surface roughness as well as the stability over temperature of this layer are also investigated. It is shown that this new passivation method is the only one simultaneously combining a low surface roughness and a high stability over long thermal anneals. In the context of SOI technology, it therefore appears as the most suitable technique for the substrate passivation of HR SOI wafers, for which a bonding between an oxidized silicon wafer and a passivated HR substrate is required.     

Stack system of PECVD amorphous silicon and PECVD silicon oxide for silicon solar cell rear side passivation

A stack of hydrogenated amorphous silicon (a‐Si) and PECVD‐silicon oxide (SiO_x) has been used as surface passivation layer for silicon wafer surfaces. Very good surface passivation could be reached leading to a surface recombination velocity (SRV) below 10 cm/s on 1 Ω cm p‐type Si wafers. By using the passivation layer system at a solar cell's rear side and applying the laser‐fired contacts (LFC) process, pointwise local rear contacts have been formed and an energy conversion efficiency of 21·7% has been obtained on p‐type FZ substrates (0·5 Ω cm). Simulations show that the effective rear SRV is in the range of 180 cm/s for the combination of metallised and passivated areas, 120 ± 30 cm/s were calculated for the passivated areas. Rear reflectivity is comparable to thermally grown silicon dioxide (SiO₂). a‐Si rear passivation appears more stable under different bias light intensities compared to thermally grown SiO₂. Copyright © 2008 John Wiley & Sons, Ltd.     

CdTe/ZnS复合钝化层对长波碲镉汞器件性能的影响研究

采用CdTe/ZnS复合钝化技术对长波HgCdTe薄膜进行表面钝化,并对钝化膜生长工艺进行了改进。采用不同钝化工艺分别制备了MIS器件和二极管器件,并进行了SEM、C-V和I-V表征分析,研究了HgCdTe/钝化层之间的界面特性及其对器件性能的影响。结果表明,钝化工艺改进后所生长的CdTe薄膜更为致密且无大的孔洞,CdTe/HgCdTe界面晶格结构有序度获得改善;采用改进的钝化工艺制备的MIS器件C-V测试曲线呈现高频特性,界面固定电荷面密度从改进前的1.671011 cm-2下降至5.691010 cm-2;采用常规钝化工艺制备的二极管器件在较高反向偏压下出现较大的表面沟道漏电流,新工艺制备的器件表面漏电现象获得了有效抑制。     

Process-induced stress and microcrack nucleation in GaAs wafers

Breakage of GaAs wafers during device fabrication leads to reduced yield and decreased quality control. Historically, wafer breakage that is not attributable to human or equipment errors has been assumed to be due to poor quality wafers. We present evidence that the probability of breakage during sub-micron GaAs device fabrication is a function of dielectric film edge stress, and not necessarily dependent on the magnitude of a critical flaw in the as-received wafer. X-ray residual stress measurements, x-ray topographic imaging, and three-point bend fracture measurements are used to determine the nature and origin of wafer breakage during those fabrication steps which induce large mechanical or thermal stresses. Our data show that the processing sequences that most influence wafer breakage are SiN passivation deposition and rapid thermal annealing implant activation. These processes are primarily responsible for large residual stresses developed in the near-surface layers of the GaAs substrate. For microelectronic applications, the existence of high film edge stresses nucleates microcracks, which further reduces fracture strength. The combined effects of high residual stress and low fracture strength make SiN passivated wafers more fragile (as compared to SiON passivated wafers), and therefore more likely to break during device processing.     

Easy-to-use surface passivation technique for bulk carrier lifetime measurements on silicon wafers

A novel, easily applicable surface passivation technique is presented, which, in combination with contactless photocoductance decay (PCD) measurements, allows a quick estimation of the bulk carrier lifetime of crystalline silicon wafers. The proposed passivation technique requires neither a chemical pre-cleaning of the silicon wafer nor expensive instrumentation. On both surfaces of the wafer a thin varnish film is deposited using a spinner. Subsequently, both surfaces of the coated silicon wafer are charged by means of a corona chamber. Using microwave-detected PCD measurements, we experimentally demonstrate that this novel surface passivation scheme provides differential surface recombination velocities in the 30–70 cm s⁻¹ range on p-as well as n-type silicon wafers. © 1998 John Wiley & Sons, Ltd.     

GaAs表面及Al_xGa_（1－x）As／GaAsHBT外基区表面（NH_4）_2S／SiN_x钝化工艺研究

分析了ＡｌｘＧａ１－ｘＡｓ／ＧａＡｓＨＢＴ外基区表面复合电流及外基区表面复合速度对直流增益的影响，用光致发光（ＰＬ）谱和Ａｌ／ＳｉＮｘ－Ｓ／ＧａＡｓＭＩＳ结构Ｃ－Ｖ特性，研究了ＧａＡｓ表面（ＮＨ４）２Ｓ／ＳｉＮｘ钝化工艺的效果及其稳定性。结果表明，ＥＣＲ－ＣＶＤ淀积ＳｉＮｘ覆盖并在Ｎ２气氛中退火有助于改善ＧａＡｓ表面硫钝化效果的稳定性。在此基础上形成了一套包括（ＮＨ４）２Ｓ处理、ＳｉＮｘＥＣＲ－ＣＶＤ淀积及退火并与现有ＨＢＴ工艺兼容的外基区表面钝化工艺，使发射区面积为４×１０μｍ２的器件增益比钝化前提高了４倍，且６０天内不退化。     

Advanced PERC and PERL production cells with 20.3% record efficiency for standard commercial p‐type silicon wafers

Following intensive research and development, Suntech Power has successfully commercialised its Pluto technology with 0.5 GW annual production capacity, delivering up to 10% performance advantage over conventional screen‐printed cells. The next generation of Pluto involves the development of improved rear surface design based on the design features of passivated emitter and rear locally diffused cells. Cells with an average efficiency over 20% were fabricated on 155 cm² commercial‐grade p‐type wafers using mass‐manufacturing processes and equipment, with the highest single‐cell efficiency independently confirmed at 20.3%. This is believed to be a record efficiency for this wafer type. Further optimisation work on contact pattern and rear surface passivation suggests the potential for further efficiency increase approaching 23%. Copyright © 2012 John Wiley & Sons, Ltd.     

热丝CVD法沉积超薄α-Si∶H钝化膜

采用热丝化学气相沉积法在n型直拉单晶硅圆片表面双面沉积厚度为10 nm的本征非晶硅(α-Si∶H)薄膜.利用光谱型椭偏测试仪和准稳态光电导法研究热丝电流、H2体积流量和热丝与衬底之间的距离对α-Si∶H薄膜结构和钝化效果的影响.结果表明,热丝电流为21.5～23.5 A时,钝化后硅片的少子寿命随着热丝电流的增加呈现先增加后降低的趋势,热丝电流为23.0A时,钝化效果最好;H2体积流量为5～ 20 cm3/min时,少子寿命随着H2体积流量的增加呈现先增加后降低的规律,体积流量为15 cm3/min时,钝化效果最好;热丝与衬底间距为4～5 cm时,随着间距的增加,薄膜的结构由晶化向非晶化转变,在间距为4.5 cm时硅片的钝化效果达到最优.