多晶硅薄膜后氢化的研究

本文利用氢气射频等离子体辉光放电技术对ａ－Ｓｉ及ｐｏｌｙ－Ｓｉ薄膜进行了后氢化研究。确定了最佳后氢化处理条件，对后氢化前后材料的电学、光学及电子态等特性进行了测量，分析，结果表明氢气射频等离子体辉光放电技术能明显改善材料的性能，利用后氢化技术对ｐｏｌｙ－Ｓｉ ＴＦＴ器件进行了处理，获得了满意的效果。     

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using $hbox{NH}_{3}$ anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide $hbox{NH}_{3}$ anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of $hbox{NH}_{3}$ anneal is related to higher N incorporation into $hbox{SiO}_{2}$ bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to $hbox{NH}_{3}$ anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.      

等离子体-热丝CVD技术制备多晶硅薄膜

采用热丝化学气相沉积和等离子体增强化学气相沉积相结合的技术制备了多晶硅薄膜,通过Raman散射、XRD、吸收谱等手段研究了薄膜结构和光学性质.结果表明,与单纯的热丝和等离子体技术相比,等离子体-热丝CVD技术在一定条件下有助于薄膜的晶化和提高薄膜均匀性.Auger谱研究表明等离子体的引入大大降低了硅化物在高温热丝表面的形成.     

等离子体-热丝CVD技术制备多晶硅薄膜

采用热丝化学气相沉积和等离子体增强化学气相沉积相结合的技术制备了多晶硅薄膜,通过Raman散射、XRD、吸收谱等手段研究了薄膜结构和光学性质.结果表明,与单纯的热丝和等离子体技术相比,等离子体-热丝CVD技术在一定条件下有助于薄膜的晶化和提高薄膜均匀性.Auger谱研究表明等离子体的引入大大降低了硅化物在高温热丝表面的形成.     

PECVD氮化硅膜氢键及硅悬挂键的研究

用红外光谱、背散射能谱和电子自旋共振波谱研究了不同淀积条件下生长的PECVD氮化硅膜中的氢键,Si/N比和硅悬挂键。对薄膜在不同温度、氮气保护下退火后的氢键及硅悬挂键的变化也进行了测试和分析。     

镀铜玻璃衬底上柱状多晶硅薄膜的制备

采用热丝化学气相沉积方法在镀铜玻璃衬底上制备了柱状多晶硅薄膜.使用XRD、Raman光谱、扫描电子显微镜(SEM)和原子力显微镜(AFM)等测试手段研究了灯丝与衬底间距(5～10 mm)、灯丝温度(1 800～1 500℃)以及对应的衬底温度(在320～200℃变化)对多晶硅薄膜的微观形貌、结晶性及晶体学生长方向的影响规律.研究结果表明:在镀铜玻璃衬底上金属诱导生长的多晶硅薄膜具有较高的晶化率,较低的晶化温度,同时铜过渡层影响多晶硅薄膜的晶体学生长方向.     

NiTiPd形状记忆合金薄膜的相变和力学特性

利用磁控溅射法制备了NiTiPd形状记忆合金薄膜,并对晶化后的薄膜测量了其相变特性和力学性能。结果表明,薄膜在真空室中于750℃热处理1 h可获得较好的形状记忆效应,NiTiPd薄膜的相变温度比相应的NiTi薄膜的相变温度高,奥氏体相变温度As高于100℃。在室温到150℃范围,随着温度升高,薄膜的断裂强度提高,但是残余应变变小。     

A Novel Nanowire Channel Poly-Si TFT Functioning as Transistor and Nonvolatile SONOS Memory

In this letter, a polycrystalline silicon thin-film transistor consisting of silicon-oxide-nitride-oxide-silicon (SONOS) stack gate dielectric and nanowire (NW) channels was investigated for the applications of transistor and nonvolatile memory. The proposed device, which is named as NW SONOS-TFT, has superior electrical characteristics of transistor, including a higher drain current, a smaller threshold voltage (V_th) , and a steeper subthreshold slope. Moreover, the NW SONOS-TFT also can exhibit high program/erase efficiency under adequate bias operation. The duality of both transistor and memory device for the NW SONOS-TFT can be attributed to the trigate structure and channel corner effect.     

Flash器件中氧化硅/氮化硅/氧化硅的特性

对普遍采用的氧化硅/氮化硅/氧化硅(ONO)三层复合结构介质层的制备工艺及特性进行了研究分析,研究了ONO的漏电特性以及顶氧(top oxide)和底氧(bottom oxide)的厚度对ONO层漏电的影响.结果表明,采用较薄的底氧和较厚的顶氧,既能保证较高的临界电场强度,又能获得较薄的等效氧化层厚度,提高耦合率,降低编程电压.     

Flash器件中氧化硅/氮化硅/氧化硅的特性

对普遍采用的氧化硅/氮化硅/氧化硅( ONO)三层复合结构介质层的制备工艺及特性进行了研究分析,研究了ONO的漏电特性以及顶氧( top oxide)和底氧( bottom oxide)的厚度对ONO层漏电的影响.结果表明,采用较薄的底氧和较厚的顶氧,既能保证较高的临界电场强度,又能获得较薄的等效氧化层厚度,提高耦合率,降低编程电压.     

Comparison of Poly-Si Thin Films Prepared by Conventional Furnace Annealing and Pulsed Rapid Thermal Annealing

Amorphous silicon films prepared by PECVD on glass substrate were crystallized by conventional furnace annealing (FA) and rapid thermal annealing ( RTA),respectively. From the Raman spectra and scanning electronic microscope(SEM),it found that the thin films made by RTA had smooth and perfect structure,while the thin films annealed by FA had a higher degree of structural disorder.     

锰铜薄膜的制备及压阻特性

为了锰铜传感器微型化,采用直流磁控溅射法制备适合高压力测量的锰铜薄膜,用X射线衍射和扫描电子显微镜技术分析了薄膜的结构和形貌,动态加载实验标定了锰铜薄膜的压阻系数。研究结果表明,晶粒尺寸决定了薄膜的压阻系数,经360℃热处理1h后,薄膜晶粒长大,压阻系数有着明显提高(K值达到0.02GPa–1),性能达到锰铜箔的水平。     

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Threshold-voltage (Vth) fluctuation due to random telegraph signal (RTS) in flash memory was observed for the first time. A large amount of data of Vth fluctuation was acquired by using a 90-nm-node memory array, and it was confirmed that a few memory cells have large RTS fluctuation exceeding 0.2 V. It was found that program-and-erase cycles increase Vth amplitude in a flash memory. It was also found by simulation and measurement that tail-bits are generated due to RTS in multilevel flash operation. The amount of Vth broadening due to the tail-bits was estimated to become larger as the scaling of memory cells advances and reaches more than 0.3 V in the 45-nm node. These results thus demonstrate that RTS will become a prominent issue in designing multilevel flash memory in the 45-nm node and beyond.     

一种高可靠大容量星载存储器的设计与研究

凭借着存储密度大和存储速率高的特点,基于NANDFlash的大容量存储器在星载存储领域得到了广泛的应用,由于NAND Flash本身存在缺陷,基于NAND Flash的大容量存储器在恶劣环境下的可靠性难以保证.提出了通过FPGA设计SRAM对关键数据三模冗余读取和缓冲、NAND Flash阵列热备份和数据的回放校验以及合理的坏块管理等措施,实现了高可靠性的大容量存储器.实验说明该系统不会因为外在偶然因素而造成数据的不完整,而且整个存储系统的成本开销相对于目前的星载存储器也非常低.     

Novel Digital Nonvolatile Memory Devices Based on Semiconducting Polymer Thin Films

Recent increases in the demand for mobile devices have stimulated the development of nonvolatile memory devices with high performance. In this Communication, we describe the fabrication of low‐cost, high‐performance, digital nonvolatile memory devices based on semiconducting polymers, poly(o‐anthranilic acid) and poly(o‐anthranilic acid‐co‐aniline). These memory devices have ground‐breaking and novel current–voltage switching characteristics. The devices are switchable in a very low voltage range (which is much less than those of all other devices reported so far) with a very high ON/OFF current ratio (which is on the order of 10⁵). The low critical voltages have the advantage for nonvolatile memory device applications of low operation voltages and hence low power consumption. With this very low power consumption, the devices demonstrate in air ambient to have very stable ON‐ and OFF‐states without any degradation for a very long time (which has been confirmed up to one year so far) and to be repeatedly written, read and erased. Our study proposes that the ON/OFF switching of the devices is mainly governed by a filament mechanism. The high ON/OFF switching ratio and stability of these devices, as well as their repeatable writing, reading and erasing capability with low power consumption, opens up the possibility of the mass production of high performance digital nonvolatile polymer memory devices with low cost. Further, these devices promise to revolutionize microelectronics by providing extremely inexpensive, lightweight, and versatile components that can be printed onto plastics, glasses or metal foils.     

Improved Electrical Characteristics and Reliability of MILC Poly-Si TFTs Using Fluorine-Ion Implantation

In this letter, fluorine-ion (F⁺) implantation was employed to improve the electrical performance of metal-induced lateral-crystallization (MILC) polycrystalline-silicon thin-film transistors (poly-Si TFTs). It was found that fluorine ions minimize effectively the trap-state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, and high on/off-current ratio. F⁺-implanted MILC TFTs also possess high immunity against the hot-carrier stress and, thereby, exhibit better reliability than that of typical MILC TFTs. Moreover, the manufacturing processes are simple (without any additional thermal-annealing step), and compatible with typical MILC poly-Si TFT fabrication processes.     

低温p-Si薄膜的制备研究

引言 近年来,有源液晶显示技术在液晶显示产业和研究领域都独占鳌头。在有源液晶显示技术中,多晶硅薄膜因高迁移率展现出独特的优势,它的器件尺寸小,可以获得更高的开口率和分辨率;由于迁移率的提高可以将周边驱动集成于显示板内部,可以有效降低材料成本,同时LCD整体的重量和厚度将会大幅度的减少。     

ITO薄膜的制备及其光电特性研究

采用直流磁控溅射法,分别用ITO陶瓷靶、In-Sn合金靶,在玻璃基片上镀膜。研究ITO透明导电膜其膜厚、靶材、溅射气压和溅射速率等工艺对光电特性的影响。结果表明,采用陶瓷靶镀膜要比合金靶效果好,膜厚70nm以上、溅射气压0.45Pa和溅射速率23nm/min左右为最佳工艺条件,并得到了ITO薄膜电阻率1.8×10–4Ω.cm、可见光透过率80%以上。     

氮化硼薄膜的场致发射特性

研究了氮化硼（BN）薄膜的场发射特性与不同基底偏压和不同膜厚的关系。在磁控溅射反应器中，使用高纯六角氮化硼（h-BN)靶，通入Ar和N2的混合气体，制备出了纳米BN薄膜。溅射是在基底加热470℃和总压力为1.2Pa的条件下进行的。在超高真空系统中测量了不同膜厚和不同基底偏压的BN薄膜的场发射特性，发现BN薄膜的场发射特性与基板偏压和膜厚关系很大。     

手持设备中焊垫材料对闪存芯片可靠性的影响

为提高用于手持设备中闪存芯片的可靠性,防止跌落的冲击力对芯片的破坏性伤害,利用试验方法及数理统计分析法对焊垫材料进行研究,为芯片制造商在选择焊垫材料时提供有益的参考。具体针对焊垫涂层为Ni/Au和OSP两种材料,跌落测试条件的严格度依次为H,G,B,F,A,E,D和C,每种样品的数量为45件,每件样品重复跌落100次。通过累积故障百分比与跌落次数的量化图解可知:Ni/Au PF的抗冲击能力较差,在H跌落测试下的故障频率是38%;而OSP PF的抗冲击能力良好,在测试条件B和测试条件F下未见故障产生。