CMOS集成电路应用讲座——第五讲 计数器及应用

CMOS计数器由触发器和门电路组成,包括同步型和非同步型两大类,计数方式有加法计数器,减法计数器,可预置数可逆计数器,可预置数1/N计数器,任意进制计数器,环形计数器等.非同步型计数器是一种串联工作的基本计数器,它的特点是结构简单,计数速度较低,因它不是受同一时钟(CL)控制下工作,所以称它为非同步型计数器.同步型计数器是一种并联工作的计数器,消除了非同步计数器累积的触发延迟,在同步型计数器中,所有触发器是在同一时钟(CL)作用下工作,所以称为同步型的,同步型计数器比非同步     

移位型计数器中反馈逻辑电路的设计

移位型计数器是以移住寄存器为主体构成的同步计数器。这类计数器具有电路连接十分简单．编码别具特色的特点，用途十分广泛。文中介绍了移位型计数器中反馈逻辑电路设计的基本思路，举例说明了移位型计数器实现的基本方法。     

设计任意模长二进制同步计数器的一种新方法

本文介绍一种设计同步计数器的新方法.它是在二进制同步计数器的基础上稍加修改即可得到所需模长的二进制同步计数器电路,其设计过程简单易行.这里所指的任意模长二进制同步计数器是指计数器符合二进制状态编码、模长小于2~n的同步计数器电路.新的设计方法则是在模长M=2~n的二进制计数器的基础上进行进行简单的修改成为所需的、任意模长的二进制同步计数器.     

基于74LS160的N进制计数器仿真设计

针对任意进制（N进制）计数器的设计目的,采用反馈复零法对基于同步十进制计数器74LS160进行设计,分别采用异步清零法实现了6进制计数器和同步置数法实现7进制计数器的设计,通过应用EWB软件对所设计的电路进行仿真实验,仿真结果表明设计的计数器能实现所要求的N进制技术功能.最终得出采用反馈复零法可以实现进制计数器的结论.     

宽带频谱稀疏信号的空时互质采样及参数估计

针对宽频段多窄带信号的联合参数估计问题,该文提出一种基于空时互质采样的频率和DOA联合估计方法。该方法基于互质采样理论,在空间上采用互质阵列模型,并对阵列中每个阵元进行时域互质采样,通过构造空时协方差矩阵产生出空时二维差分有限阵列来完成空频联合估计。此方法可以极大地提高空时域的可探测目标数。另外,该文推导了空时互质参数的最优选取准则。仿真结果验证了此方法的正确性和有效性。      

异步计数器的一种简单设计方法

我们的“电子技术”课程使用华中工学院编的教材。教材中对同步计数器的设计方法作了详细介绍而对非二进制异步计数器则涉及很少。而异步计数器在工业自动化领域内使用较多。因此我们在教学实践中作了一些探讨。即把同步计数的设计方法搬来使用。结果表明设计一个非二进制异步计数器比设计一个非二进制同计数器还简便得多。在学生学完非二进制同步计数器的设计之后,再加一个学时即可掌握非二进制异步计数器的设计。这里,原将它     

具有四个输出并基于微处理器的双定时器

基于Freescale半导体公司MCC908QY型8位闪存微型计算机的图1所示电路，可提供一个低成本通用双定时器．该定时器可代替单触发电路。您可以通过修改汇编语言软件来满足特定应用要求。该电路采用微处理器IC1的内部12．8MHz时钟振荡器。内部时钟除以4即获得3．2MHz时钟频率，此频率进一步除以定时器预定比例64即获得50kHz时钟。将定时器模数计数器除以50000．可获得可产生1次／秒实时中断与主定时间隔的1Hz时基。     

同步十进制计数器CT4160及其应用

本文根据置位法和复位法提出了用同步十进制计数器和四位超前进位全加器构成的任意进制计数器。此外，用BCD码十进制计数器和八选一数据选择器还构成了任意码制十进制计数器。     

互质阵列DOA估计性能综合分析北大核心CSCD

互质阵列是近年来兴起的新型阵列,能显著提高阵列自由度,处理信源数大于阵元数时的波达方向(DOA)估计,且能提高角度分辨率和测角精度。文中根据互质阵物理阵元和虚拟阵元特点,结合多重信号分类(MUSIC)算法提出适用于互质阵基于物理阵列和虚拟阵列的DOA估计方法。该方法以非相干信号源为研究对象,利用互质阵列建立信号接收模型,基于物理阵列的DOA估计方法根据互质阵物理阵元位置特点推导其导向矢量,然后根据导向矢量计算回波信号数据和信号协方差矩阵,最后利用MUSIC算法进行DOA估计。基于虚拟阵列的DOA估计方法根据其虚拟阵元数据特点在向量化协方差矩阵并去冗余后选取连续虚拟阵元接收数据,然后对新协方差矩阵进行一维Toeplitz平滑重构,最后利用MUSIC算法或求根MUSIC算法进行DOA估计。与等阵元数的均匀线阵进行对比,仿真实验验证了互质阵列DOA估计性能的优越性。     

基于CAN总线的并联式多逆变器风电并网控制系统

为了实现多逆变器并联风电系统信息交互和同步控制,提出了基于CAN总线的多逆变器并联风电并网系统控制方法。建立了共直流母线并联型拓扑的等效平均模型,利用CAN总线控制各逆变器正弦参考电压的幅值以均分并网功率。采用TMS320F28335实现全数字化并联风电系统设计,并基于55kW永磁风电样机对所提方法进行性能验证。实验表明,CAN总线同步驱动方法保证了多逆变器并联系统的数据交互性和同步性。     

基于Multisim的集成计数器及应用逻辑功能的仿真

在数字电路的教学中,集成计数器是一个重点无疑也是一个教学难点.本文以典型的74LS161N同步四位二进制计数器为例,用Multisim12软件对其进行功能仿真,并运用反馈清零法和反馈置数法设计十进制计数器,用同步和异步级联设计六十进制计数器来讲述任意进制计数器的设计方法,该设计方法灵活直观,可以非常直观的将电路和输出状态展现在屏幕上.通过该方法的学习,可加深学生对计数器的理解,提高学生的电路设计和实践动手能力.     

A compact high-speed (31,5) parallel counter circuit based oncapacitive threshold-logic gates

A novel high-speed circuit implementation of the (31,5)-parallel counter (i.e., population counter) based on capacitive threshold logic (CTL) is presented. The circuit consists of 20 threshold logic gates arranged in two stages, i.e., the parallel counter described here has an effective logic depth of two. The charge-based CTL gates are essentially dynamic circuits which require a periodic refresh or precharge cycle, but unlike conventional dynamic CMOS gates, the circuit can be operated in synchronous as well as in asynchronous mode. The counter circuit is implemented using conventional 1.2 μm double-poly CMOS technology, and it occupies a silicon area of about 0.08 mm². Extensive post-layout simulations indicate that the circuit has a typical input-to-output propagation delay of less than 3 ns, and the test circuit is shown to operate reliably when consecutive 31-b input vectors are applied at a rate of up to 16 Mvectors/s. With its demonstrated data processing capability of about 500 Mb/s, the CTL-based (31,5) parallel counter offers a number of application possibilities, e.g., in high-speed parallel multiplier arrays and data encoding circuits     

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18- $muhbox{m}$ CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.      

PCM串行数据流同步时钟提取设计

为了产生语音调度系统中数据接收端异步接收PCM30／32路一次群串行数提流所需同步时置瑚目的,采用以分频计数器为基础模块,辅以相位校正和误校正处理模块从已知速率PCM数据流中提取同步时钟信号的方法,利用可编程逻辑器件和VerilogHDL硬件描述语言对该方法进行实现和仿真验证。结果表明该方法能够有效地利用已有串行数据流产生具备合适相位的同步采样时钟信号。     

Two analog counters for neural network implementation

Simple analog circuits which are useful for the implementation of the synchronous Boltzmann machine learning algorithms are presented. A simple charge-transfer-based analog counter is described. The authors give a functional model of its behavior and analyze the differences between this model and the counter implementation. They also present simulation results and the test of a prototype. Along the same lines, they study a switched-current-based counter, which achieves better results (dynamic range, linearity) through higher complexity     

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-typeflip-flops

A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 μm CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage     

三维同步荧光结合平行因子算法研究丹参粉的荧光特征

具有几十余种化学成分的丹参粉是典型的多组分物质,应用传统二维荧光光谱难以对其作定量分析。为了研究多组分共存的丹参粉水溶液的荧光特征,利用三维同步荧光光谱法结合平行因子分析法(PARAFAC)、分半信度法(split half method)、残差平方和(sum of squared error),解析光谱重叠严重的丹参粉水溶液荧光光谱。经上述方法分析确定丹参粉水溶液的平行因子模型组分数为4,其相应组分荧光特征为:第1组分荧光特征λ_Ex=470~480 nm,λ_Em=520~530 nm;第2组分荧光特征λ_Ex=400~410 nm,λ_Em=490~500 nm;第3组分荧光特征λ_Ex=370~380 nm,λ_Em=460~470 nm;第4组分荧光特征λ_Ex=560~570 nm,λ_Em=620~630 nm。其中第2组分的荧光特征可能是丹酚酸B的荧光特征。实验结果表明,在多组分共存且有较多干扰物质时,三维同步荧光结合平行因子算法可以简化光谱分析,较好地表征丹参的整体荧光特性。本研究为多组分共存的中药材分析提供了建议与帮助。     

Efficient CMOS counter circuits

Several efficient counters are presented. A nine-transistor divide-by-two circuit is used as a basic building block. With transistor sizing, an input frequency of 400 MHz can be adopted by an asynchronous counter, while an eight-bit synchronous counter can achieve clock rates of more than 200 MHz in a 3-μm CMOS process. The power consumption of the proposed precharged dynamic synchronous counter is reduced to almost half as much as normal