小片CMOS驱动电路的倒装焊In柱阵列沉积

本文研究了在用于GaAs/AlGaAs多量子阱空间光调制器驱动电路小片芯片上进行In柱阵列沉积的方法。使用了带有中央通孔的甩胶套进行甩胶,可以将驱动电路小片上1000um宽的胶边减小至500um,有效保证了沉积In柱阵列的完整性。使用此方法,64x64,20um高,30um直径的In柱阵列能够完整沉积在5mmx6.5mm的CMOS驱动电路上。     

Indium bump array fabrication on small CMOS circuit for flip-chip bonding

We demonstrate a novel method for indium bump fabrication on a small CMOS circuit chip that is to be flip-chip bonded with a GaAs/AlGaAs multiple quantum well spatial light modulator.A chip holder with a via hole is used to coat the photoresist for indium bump lift-off.The 1000μm-wide photoresist edge bead around the circuit chip can be reduced to less than 500μm,which ensures the integrity of the indium bump array.64×64 indium arrays with 20μm-high,30μm-diameter bumps are successfully formed on a 5×6.5 mm~2 CMOS chip.     

Fabrication of 0.95Sn−0.05Au solder micro-bumps for flip-chip bonding

This letter describes the successful fabrication of a 0.95Sn−0.05Au solder microbump on a compound semiconductor wafer by reflowing of multi-layer metal film. Since the inherent interdiffusion in Au−Sn phases results in the alloying of multi-layer films, the composition of micro-bump is well controlled by the thickness of constituent metal films. The micro-bumps melt at about 220 C, which is close to the lowest eutectic temperature in a Au−Sn system. Solder bonding using 0.95Sn−0.05Au micro-bump is a very useful technique for the flipchip bonding of compound semiconductor devices.     

Effect of surface finish on the failure mechanisms of flip-chip solder joints under electromigration

Two substrate surface finishes, Au/Ni and organic solderable preservative (OSP), were used to study the effect of the surface finish on the reliability of flip-chip solder joints under electromigration at 150°C ambient temperature. The solder used was eutectic PbSn, and the applied current density was 5×10³ A/cm² at the contact window of the chip. The under bump metallurgy (UBM) on the chip was sputtered Cu/Ni. It was found that the mean-time-to-failure (MTTF) of the OSP joints was six times better than that of the Au/Ni joints (3080 h vs. 500 h). Microstructure examinations uncovered that the combined effect of current crowding and the accompanying local Joule heating accelerated the local Ni UBM consumption near the point of electron entrance. Once Ni was depleted at a certain region, this region became nonconductive, and the flow of the electrons was diverted to the neighboring region. This neighboring region then became the place where electrons entered the joint, and the local Ni UBM consumption was accelerated. This process repeated itself, and the Ni-depleted region extended further on, creating an ever-larger nonconductive region. The solder joint eventually, failed when the nonconductive region became too large, making the effective current density very high. Accordingly, the key factor determining the MTTF was the Ni consumption rate. The joints with the OSP surface finish had a longer MTTF because Cu released from the substrate was able to reduce the Ni consumption rate.     

The application of flip-chip bonding interconnection technique on the module assembly of 10 Gbps laser diode

Flip chip bonding technique using Pb/In solder bumps was applied to packaging of a 10 Gbps laser diode (LD) submodule for high speed optical communication systems. The effect of the flip-chip bonding interconnection technique instead of conventional wire bonding was investigated for high speed broad band devices. The broad band performance of 10 Gbps LD submodule was simulated using SPICE S/W and compared with experimental results. In this simulation, the 10 Gbps LD was modeled in a parallel RC circuit. The values of R and C used for the equivalent circuit were 5ω and 1 pF, respectively. The LD was placed in series with a 18ω thin film resistor to prevent the impedance mismatch between the LD and a 25ω transmission line. The dependence of parasitic parameters on the small signal modulation bandwidth and the scattering parameters of the LD submodule was investigated and analyzed up to 20 GHz. A small signal modulation bandwidth of 14 GHz at 10 mA dc bias current and the clean modulation response up to 20 GHz were found for the flip-chip bonded submodule. The bandwidth of flip-chip bonded 10 Gbps LD submodule is wider than that of the wire-bonded LD submodule by a difference of 3.8 GHz.     

Thermosonic bonding of lead-free solder with metal bump for flip-chip bonding

While extensive research on the lead-free solder has been conducted, the high melting temperature of the lead-free solder has detrimental effects on the packages. Thermosonic bonding between metal bumps and lead-free solder using the longitudinal ultrasonic is investigated through numerical analysis and experiments for low-temperature soldering. The results of numerical calculation and measured viscoelastic properties show that a substantial amount of heat is generated in the solder bump due to viscoelastic heating. When the Au bump is thermosonically bonded to the lead-free solder bump (Sn-3%Ag-0.5%Cu), the entire Au bump is dissolved rapidly into the solder within 1 sec, which is caused by the scrubbing action of the ultrasonic. More reliable solder joints are obtained using the Cu/Ni/Au bump, which can be applied to flip-chip bonding.     

Experimental observations on nonlinear phenomena in transducer assembly for thermosonic Flip-Chip bonding

Dynamical characteristics of PZT actuated transducer assembly are the key to reliable flip-chip bonding and basic understanding of metal interconnection. A systematic experimental observations and analysis clearly exhibit that, rich phenomena and effects like the negative cubic stiffness, dynamical coupling between transducer body and tool, velocity dropping and anomalous phase portrait of the die movement, may be explained by nonlinear features and non-parallel loading of transducer assembly onto its bonding area. It will be possible to explore their mechanism and effects to bonding quality by identifying and decoding them.     

Increasing the bonding strength of chips on flex substrates using thermosonic flip-chip bonding process with nonconductive paste

Thermosonic flip-chip bonding process with a nonconductive paste (NCP) was employed to improve the processability and bonding strength of the flip-chip onto flex substrates (FCOF). A non-conductive paste was deposited on the surface of the copper electrodes over the flex substrate, and a chip with eight gold bumps bonded onto the copper electrodes by the thermosonic flip-chip bonding process.For the chips and flex substrates assembly, ultrasonic power is important in the removal of some of the non-conductive paste on the surface of copper electrodes during thermosonic bonding. Accordingly, gold stud bumps in this study were directly bonded onto copper electrodes to form successful electrical paths between chips and the flex substrate. A particular ultrasonic power resulted in some metallurgical bonding between the gold bumps and the copper electrodes, increasing the bonding strength. The ultrasonic power was not only to remove the NCP from the copper electrodes, but also formed metallurgical bonds during the thermosonic flip-chip bonding process with NCP.In this study, the parameters of the bonding of chips onto flex substrates using thermosonic flip-chip bonding process with NCP were a bonding force of 4.9 N, a curing time of 40 s, a curing temperature of 140 °C and an ultrasonic power of 14.46 W. The processability and bonding strength of flip-chips on flex substrates using thermosonic bonding process with NCP was verified in this study. This process has great potential to be applied to the packaging of consumed electronic products.     

Recent advances in modeling the underfill process in flip-chip packaging

Flip-chip underfill process is a very important step in the flip-chip packaging technology because of its great impact on the reliability of the electronic devices. In this technology, underfill is used to redistribute the thermo-mechanical stress generated from the mismatch of the coefficient of thermal expansion between silicon die and organic substrate for increasing the reliability of flip-chip packaging. In this article, the models which have been used to describe the properties of underfill flow driven by capillary action are discussed. The models included apply to Newtonian and non-Newtonian behavior with and without the solder bump resistance for the purpose of understanding the behavior of underfill flow in flip-chip packaging.     

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

A novel lead-free flip-chip technology for mounting high-speed compound semiconductor ICs, which have a relatively severe limitation regarding high-heat treatment, is presented. Solder bump interconnections of 0.95Sn-0.05Au were successfully fabricated by reflowing multilayer metal film at as low a temperature as 220/spl deg/C. The bumps were designed to have a diameter of 36 /spl mu/m with a gap between the chip and the motherboard of 24 /spl mu/m. The electrical characteristics of flip-chip-mounted coplanar waveguide chips were measured. The deterioration in reflection loss in the flip chip mounting was less than 3 dB for frequencies up to W-band.     

圆片级低温富锡金锡键合

Sn-rich Au–Sn solder bonding has been systematically investigated for low cost and low temperature wafer-level packaging of high-end MEMS devices.The AuSn2 phase with the highest Vickers-hardness among the four stable intermetallic compounds of the Au–Sn system makes a major contribution to the high bonding shear strength.The maximum shear strength of 64 MPa and a leak rate lower than 4.9×10-7 atm·cc/s have been obtained for Au46Sn54 solder bonded at 310 ℃.This wafer-level low cost bonding technique with high bonding strength can be applied to MEMS devices requiring low temperature packaging.     

Thermosonic flip-chip bonding for SAW filter

A flip-chip bonding (FCB) method suitable for the surface acoustic wave (SAW) filter was developed. In this method, the gold-ball bumps formed on the chip are directly bonded onto the ceramic substrate by thermosonic bonding. After FCB, they are sealed with a cap without using underfill resin. To obtain high bond strength, characteristic properties of the substrate electrode and the ball bump, were optimized. Furthermore, bondability has been improved by adopting a ramp-up loading profile. The reliability test was carried out with 6-pin SAW chips, and we confirmed the sufficient reliability of bonds.     

Low-k compatible all-copper flip-chip connections

A novel fabrication technique using electroless copper deposition has been used to produce all-copper, chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on the chip and substrate. The electroless copper joints were annealed at 180 °C after plating. A model was developed to explore methods for lowering the stress within the copper pillar, especially at the point where the pillar intersects the chip surface. The acceptable stress level within the copper pillars is a function of the on-chip dielectric material and the on-chip interconnect structures. In order to avoid fracture of the on-chip dielectric, the stress in the copper pillars should be less than the current lead-free solders that the all-copper pillars would be replacing. A polymer collar surrounding the copper pillars was used to support the pillars and improves thermo-mechanical reliability. The improvement in stress-reduction, ultimately leading to higher reliability was studied as a function of elastic modulus of the polymer collar support. It has been shown that the pillar stress generated during temperature cycling can be reduced by increasing the modulus of the pillar support and changing the shape of the copper pillars. Finally, three high-contrast photodefinable collar materials were characterized and tested. Nano-indentation experiments were performed to measure the mechanical properties of each material and shear tests were performed to verify the benefits of the higher elastic modulus collars.     

Stress-strain curves of flip-chip solder balls based on finite-element modeling of thermal displacements measured by electronic speckle pattern interferometry

Electronic speckle pattern interferometry (ESPI) was applied to noncontact, real-time evaluation of thermal deformation in a flip-chip solder joint. To measure the deformation of such tiny components as the solder balls in the flip-chip, the spatial resolution of ESPI was increased to submicron scale by magnifying the areas studied. Experimental-computational procedures were developed to obtain stress-strain curves for solder balls in the flip-chip based on finite-element modeling (FEM) of in-plane ESPI thermal displacement data. The stress-strain curve obtained for the flip-chip solder was compared with those for bulk solder. The microstructure was also studied to clarify the stress-strain curve results.     

Thermal characteristics evaluation for board-level high performance flip-chip package equipped with vapor chamber as heat spreader

Thermal analysis was performed in this work to compare the thermal performance of a board-level high performance flip-chip ball grid array package equipped with solid Cu or vapor chamber (VC) as the heat spreader and Al-filler gel or In solder as the thermal interface material (TIM). The effect of different heat source sizes was also examined. Numerical results indicate that for the particular test vehicle under a power dissipation of 160 W, the thermal performance is remarkably enhanced by switching TIM from Al-filler gel to In solder while the enhancement by using VC instead of solid Cu heat spreader is only observable when In solder is incorporated. Moreover, the performance of VC gradually enhances then retards as the heat source size decreases. The retardation can be attributed to the more dominant role of die in heat dissipation when the heat source size gradually shrinks.     

微流控分析芯片制作中的低温键合技术

微流控分析芯片制作方法的研究是微流控分析的基础。制作性能良好的微流控分析芯片时,基片与盖片的键合技术十分重要。本文针对近年来发展迅速的低温键合技术,对各种方法进行了评价,并对其发展前景进行了展望。     

Gas flow simulations of a fluxless Si solder bonding oven

In this paper the technology of the “Linn” type Si fluxless solder bonding oven and gas flow simulations of the oven are discussed. This oven is used for fixing silicon chips on metal substrates with high temperature solder bonding process. The solder is applied in a foil form which is placed between the Si chip and the metal substrate. This does not contain any flux, therefore a reducing agent has to be applied to avoid the oxidation of the joints during the soldering process. In this technology the reducing agent is the Forming gas which is a mixture of 10 vol.% H₂ and 90 vol.% N₂. The key factors of this soldering process was studied which are the suitable temperature (350-370 °C for 13-15 min) and the adequate H₂ concentration (8-10 vol.%). A detailed 3D gas flow model of the Linn oven was prepared which is based on the finite volume model (FVM) method. The thermal and gas flow circumstances - used the basic and new theoretical oven settings - were compared by simulations applied the ANSYS-FLUENT system. The gas flow model was verified by the measurements of the H₂ concentration, the temperature and the pressure inside the oven. The aim was to find new oven settings in order to improve the mechanical stability and decrease the void percent of the solder joints.     

Electromigration-induced failure in flip-chip solder joints

The electromigration failure mechanism in flip-chip solder joints through the rapid dissolution of the Cu metallization was studied in detail. The ambient temperature was found to be a very important factor in this failure mechanism. When the ambient temperature was changed from 100°C to 70°C, the time to failure changed from 95 min to 31 days. The results of this study indicate that temperature, as an experimental variable, is not less important than the current density in electromigration study. The surface temperatures of the chip and substrate during electromigration were also measured. The temperature of the Si chip was reasonably homogeneous because of the fact that Si is a very good thermal conductor. It was also reasoned that the high thermal conductivity of the PbSn solder could not support a temperature gradient large enough to induce thermomigration across the solder joint in the present study. Experimentally, no evidence of mass transport caused by thermomigration was observed.     

Modeling and evaluation criterion for thermocompression flip-chip bonding

A single joint finite element model (FEM) using a newly developed configuration independent evaluation criterion has been created, and experimentally verified, to provide more accurate predictions of bond formation based on the joint design and assembly process parameters. This model is based on the joint interface mechanics resulting from joint bump compression. Previous studies used a deformation criterion that depended on a specific joint configuration to evaluate the effectiveness of the expected bond. This limited the applicability of the model results to the joint design for which the deformation criterion had been experimentally determined. The technique reported in this research, uses finite element models to compute detailed distributions of stresses/strains at the interface of a joint when it is plastically deformed under compression. The evaluation criterion is defined to be the change in the differential area at the bonding interface, and is shown mathematically as follows: /spl Delta/A=/spl epsi//sub xx/+/spl epsi//sub yy//spl ges/(/spl epsi//sub xx/+/spl epsi//sub yy/)/sub crit/. Models using this criterion allow for the comparison of the effects of various joint design and manufacturing process parameters on the bond joint mechanics, and the resulting probable bond joint quality. A determination of the minimum deformation required for joint formation can be obtained for any design within specified limits.     

Interfacial Reaction Between Eutectic Sn-Pb Solder and Electroplated-Ni as well as Electroless-Ni Metallization During Reflow

Electroplated-Ni (EP-Ni) has been adopted gradually as an underbump metallization layer due to its comparatively lower resistivity and higher deposition rate. In this study, the metallurgical reaction between eutectic Sn-Pb solder and EP-Ni as well as electroless-Ni (EL-Ni) was investigated at 200°C, 210°C, 220°C, and 240°C. It is found that the growth rate of Ni₃Sn₄ intermetallic compound (IMC) on EP-Ni was slower than that on EL-Ni. The consumption rate is measured to be 0.97 × 10⁻³ μm/s and 1.48 × 10⁻³ μm/s for EP-Ni and EL-Ni, respectively. The activation energy is determined to be 51 kJ/mol and 48 kJ/mol for EP-Ni and EL-Ni, respectively. The dense structure of EP-Ni may be responsible for the lower IMC formation rate.