A new five-parameter MOS transistor mismatch model

A new five-parameter MOS transistor mismatch model is introduced capable of predicting transistor mismatch with very high accuracy for ohmic and saturation regions, including short-channel transistors. The new model is based on splitting the contribution of the mobility degradation parameter mismatch Δ&thetas; into two components, and modulating them as the transistor transitions from ohmic to saturation regions. The model is tested for a wide range of transistor sizes (30), and shows excellent precision, never reported before for such a wide range of transistor sizes, including short-channel transistors     

Optimizing MOS transistor mismatch

An investigation of MOS transistor mismatch is undertaken and a methodology is developed for optimizing mismatch without increasing layout area. Dramatic improvements of up to 300% in matching can be realized by selecting the optimum W/L ratio without changing the overall WL area product. The theoretical basis for the obtainable improvements is fully described and an expression is derived and verified by experiment to predict the W/L ratio which gives optimum matching     

An MOS transistor model for analog circuit design

This paper presents a physically based model for the metal-oxide-semiconductor (MOS) transistor suitable for analysis and design of analog integrated circuits. Static and dynamic characteristics of the MOS field-effect transistor are accurately described by single-piece functions of two saturation currents in all regions of operation. Simple expressions for the transconductance-to-current ratio, the drain-to-source saturation voltage, and the cutoff frequency in terms of the inversion level are given. The design of a common-source amplifier illustrates the application of the proposed model     

An accurate large-signal MOS transistor model for use in computer-aided design

Some MOS transistor models for computer-aided design, each having a given accuracy and complexity, are presented. These models apply before saturation and in the saturation region. Before saturation, the proposed theory takes into account the behavior of mobility versus gate-channel and drain-source biases. In the saturation region the effect of mobile carriers on the drain-channel space-charge layer in an approximate two-dimensional analysis is taken into account. This model has been checked for dc characteristicsI_{D} (V_{DS})and different channel lengths, dynamic resistances in the saturation region, transfer characteristics of various inverters, and dynamic response of these circuits. The accuracy is within 5 percent.     

A simple model for the MOS transistor in saturation

A model is proposed that takes into account mobility reduction, carrier velocity saturation effects and length modulation for an NMOS transistor. The model ensures continuity of output conductance and its derivative with respect to the drain voltage at the onset of saturation and is made simple by the use of empirical formulas for the drain current in both linear and saturation regions.     

A charge-based model for short-channel MOS transistor capacitances

A model that conserves charge, is valid in the strong inversion regime, and is based on the quasi-static approximation is presented. Major second-order effects such as carrier velocity saturation, mobility degradation, and channel-length modulation are included in the derivation of current and charges. The theoretical predictions of the model are compared to both experimental and numerically simulated data and are found to be in good agreement over a wide range of gate and drain voltages and to confirm many properties that have been observed or predicted     

MOS power transistor model for Electromagnetic Susceptibility analysis

This paper deals with the susceptibility of MOS power transistors to radio frequency interference. An nMOS connected in the low-side configuration is considered and the failures that result from disturbances superimposed onto the drain-source nominal signal are discussed. The susceptibility of power transistors to electromagnetic interference is analyzed referring to small-signal equivalent circuits and the influence of the gate-source input loop impedance is highlighted. To these purpose a distributed gate resistance model is used in small-signal analysis and time domain simulations. The results obtained with this model are in a much better agreement with the experimental results than those obtained with commonly used lumped models are. On the basis of these investigations some technology and design solutions are proposed to reduce the susceptibility to electro-magnetic disturbances affecting the drain-source terminals of a power MOS transistor connected in the low-side configuration.     

Accurate two sections model for MOS transistor in saturation

In this paper an experimental and theoretical analysis of the characteristics of MOS transistors in saturation is presented. The experimental study of the drain current and output resistance brought to light a hitherto undescribed property of the product (R_D.I_D)². Based on this property a model is developed in which the channel is assumed to be divided into two regions. This model enables one, by means of a simple algorithmic calculation, to simulate the dependence of the drain current or of the output resistance as a function of the bias voltages. The continuity of these characteristics with those provided by the approximation of the gradual region is ensured. The experimental methods of determining the parameters acting on the saturation resisrance, as well as their main properties, are described.     

Direct extraction of MOS transistor model parameters

The direct extraction method of MOS transistor parameters is summarized and results from its application to the first Norchip 1µm CMOS process run are presented. Two different transistor models (SPICE level 3 and BSIM) have been used, and both models are found to be useful at least down to 1µm devices: typical average relative errors between measured and calculated currents are in the 2-9% range. Two methods of calculating the difference between drawn and effective geometries have been compared. The influence of the source/drain series resistance is also discussed.     

A table MOS transistor model parameter control

The method for MOS transistor parameter control of submicron MOS transistors, which uses the results of standard electronic testing carried out while monitoring the VLSI manufacturing process, is suggested.     

A physically-based MOS transistor avalanche breakdown model

A physically based breakdown model for MOSFET's is presented to rectify the unexplained experimental breakdown behaviors. The drain avalanche breakdown in the MOS transistor can be caused by either infinite multiplication (MI) or finite multiplication with positive feedback of the substrate current (MF) due to the impact ionization in the pinch-off region. The breakdown voltages of these two modes of breakdown have different dependencies on the biasing conditions and device parameters. For MI mode of breakdown, the breakdown voltage increases slowly with the gate voltage and can be approximated by the drain saturation voltage plus a constant offset. For MF mode of breakdown, the breakdown voltage decreases as the drain saturation current becomes larger. The calculated breakdown characteristics agree well with the measured ones for devices with effective channel length in the range of 0.44~10 μm     

Single transistor MOS RAM using a short-channel MOS transistor

The relationship between sensitivity and other factors in the sense circuit of a single transistor MOS RAM has been investigated by computer simulation. An expression for sensitivity of the sense circuit has been derived. It suggests key points to increase the sensitivity of the sense circuit. A new sense circuit that defects a signal less than /spl plusmn/30 mV and has low power capability 50 /spl mu/W/circuit is realized by following the suggestions. The high performance of the proposed sense circuit has been verified through the fabrication of a 1K MOS RAM. Fine pattern technology, such as 2-/spl mu/m minimum pattern width and spacing and 500-/spl Aring/ gate oxide thickness, has been adopted. The threshold voltage of the MOS transistor is 0.8 V and dc supplies are 7 V and /spl plusmn/2 V. This 1K RAM has characteristics of 80-ns access time, 150-ns cycle time, and 30-mW power dissipation.     

An accurate two-dimensional numerical analysis of the MOS transistor

A two dimensional numerical analysis has been made for MOS transistors with both small and large values of channel lenghts and various bias conditions. Results are compared with a simplified analysis of the MOST and with experimental data obtained on devices. Detailed pictures of the free carriers density distribution and of the voltage distribution are presented for various channel lengths and two dimensional effects are clearly seen near the source and the drain that are very hardly accounted for in a simplified one dimensional analysis. Such a program seems to be a very powerful tool for device optimisation and physical understanding of the behaviour of very small devices used in complex circuits.     

Procedure for building a MOS transistor high frequency small-signal model

This paper examines a procedure for building a MOS transistor small-signal equivalent circuit for the high frequency range. Procedures are proposed for determining the ac and dc parameters. The simulation results and experimental data are also presented.     

Deep-channel MOS transistor

A new type of ion-implanted MOS transistor is described. The transistor functions, for example, as an integrating nondestructively readable photosensor and its technology is fully compatible with the advanced MOS integrated circuits.     

Evaluation of surface-potential-based bulk-charge compact MOS transistor model

The existing surface-potential-based compact metal-oxide-semiconductor transistor models are based on the 1978 Brews delta-function charge-sheet approximation, which was derived empirically from the 1966 Pao-Sah drift-diffusion double integral formula. This paper provides a device physics-based derivation of a surface-potential-based compact model by analytical approximation of the double and single bulk-charge integrals of the four one-dimensional components of the six-component 1996 Sah two-dimensional formula. In this compact model development, the mobile carrier-space-charge-limited parabolic-drift and linear-diffusion current components are analytically represented by the surface potential without approximation, while the immobile-impurity bulk-space-charge-limited double-integral drift-current and single-integral diffusion-current components are evaluated analytically using three possible surface-potential compact model approximations. This paper calculates the accuracy of these approximate analytical bulk-charge-limited drift and diffusion current components in both the inversion and subthreshold ranges and discusses factors that affect the accuracy in the subthreshold range and near flatband.     

Negative-resistance MOS transistor

The author proposes a novel approach for implementing a negative-resistance MOSFET that uses a non-uniform drain-current flow within one integrated structure. This MOS device exhibits a negative output conductance within a specific bias range as a consequence of current sharing between two MOSFETs of different geometries. The author describes a negative-resistance MOS transistor and discusses in detail its principle of operation, design, and electrical characteristics. The MOSFET is a three-terminal voltage-controlled device that consists of two MOS transistors with the same type of channel conductivities and can be implemented either in n-channel or p-channel versions. The proposed device is a compact element that can be fabricated together with other semiconductor devices using a standard CMOS technology     

MOS晶体管技术

简要回顾MOS晶体管一些具有代表性的技术进展,分析了其在将来超大规模集成电路(ULSI)应用中的主要限制.从材料以及器件结构两个方向分别阐述了突破现有MOS技术而最有希望被将来ULSI工业所采用的新型晶体管技术.     

On the short-channel theory for MOS transistor

An attempt is made to derive rigorous analysis for the short-channel MOS transistor on the basis of the 2-D Poisson's equation. The analysis is able to predict a correct dependence of the threshold voltage on channel length and drain voltage, avoids the need for the definition of an average depletion charge density, and gives more physical insight into the short-channel effects