Manufacturing costs for microsystems/MEMS using high aspect ratio microfabrication techniques

The emphasis on high aspect ratio micromachining techniques for microsystems/MEMS has been mainly to achieve novel devices with, for example, high sensing or actuation performance. Often these utilize deep structures (100–1,000 μm) with vertical wall layers but with relatively modest spatial resolution (1–10 μm). As these techniques move from research to industrial manufacture, the capital cost of the equipment and the cost of device manufacture become important, particularly where more than one micromachining technique can meet the performance requirements. This paper investigates the layer-processing costs associated with the principal high aspect ratio micromachining techniques used in microsystems/MEMS fabrication, particularly silicon surface micromachining, wet bulk etching, wafer bonding, Deep Reactive Ion Etching, excimer laser micromachining, UV LIGA and X-ray LIGA. A cost model (MEMSCOST) has been developed which takes the financial, operational and machine-dependent parameters of the different manufacturing techniques as inputs and calculates the layer-processing costs at the wafer and chip level as a function of demand volume. The associated operational and investment costs are also calculated. Cost reductions through increases in the wafer size and decreases in chip area are investigated, and the importance of packaging costs demonstrated.     

Development of an assembly process and reliability investigations for flip-chip LEDs using the AuSn soldering

 A packaging process for flip-chip LEDs (light emitting diodes) is described. The LEDs are picked and placed on a silicon substrate wafer. After reflow the substrates are individualized. AuSn solder is used for the interconnection. The solder compounds, Au and Sn, are electroplated separately: Sn on the silicon substrate and Au on the chip. The interconnections formed by tin-rich and by gold-rich intermetallic phases are compared. The metallurgy and the reliability of the LEDs are investigated. The superiority of the gold-rich interconnection is demonstrated. Received: 30 May 2001 / Accepted: 17 July 2001     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

A new approach for handling and transferring of thin semiconductor materials

 Based on the fracture mechanics analysis of crack propagation, the phenomenon of subcritical crack growth was utilized for a controlled debonding of directly wafer-bonded interfaces. The approach allowed the well-defined separation of bonded wafers although the bond strength was high due to thermal annealing. The achieved splitting velocity depended on the wafer material, the wafer thickness ratio, the bonding process parameters, and the environmental conditions during cleaving. In combination with wafer bonding, the method can be used for a temporary stiffening and handling of thin and brittle wafers during fabrication, even if the wafers are exposed to high process temperatures. The approach can also be applied to fabricate micromechanical systems (MEMS). Received: 12 July 2001/Accepted: 26 February 2002 This paper was presented at the Conference of Micro System Technologies 2001 in March 2001.     

Pneumatically bidirectional microfluidic regulation using Venturi pumps by deep RIE and bonding technology

 A novel design for bidirectional fluidic motion has been demonstrated which is widely used in the biochip or microfluidic component. Two miniaturized Venturi pumps as well as pneumatic servo system are designed to easily control the bidirectional fluidic motion by simple fabrication. The pumping velocity is 0.86 μl/min at a 2.75 slpm (standard liter per minute) air flow read from mass flow controller (MFC) for totally 4.3 μl blue ink in a 300 μm wide by 300 μm deep channel. The higher airflow, the faster fluidic pumping speed. Numerical simulation is performed to correlate the experimental data of fluidic speed and air flow in microchannel. The test chip with two Venturi pumps and channel was batchedly fabricated by silicon deep reactive ion etching (RIE) and glass anodic bonding. The ICP LIGA process is also investigated after deep RIE followed the electroforming and hot embossing. Received: 10 August 2001/Accepted: 24 September 2001     

Focussed ion beam based fabrication of micro-electro-mechanical resonators

A simple and fast process to fabricate micro-electro-mechanical (MEM) resonators with deep sub-micron transduction gaps in thin SOI is presented. The proposed process is realized on both 350 nm and 1.5 μm thin silicon-on-insulator (SOI) substrates, evaluating the possibilities for MEMS devices on thin SOI for future co-integration with CMOS circuitry on a single chip. Through the combination of conventional UV-lithography and focused ion beam (FIB) milling the process needs only two lithography steps, achieving ∼100 nm gaps, thus ensuring an effective transduction. Different FIB parameters and etching parameters and their effect on the process are reported.     

Stamp-and-stick room-temperature bonding technique for microdevices

Multilayer MEMS and microfluidic designs using diverse materials demand separate fabrication of device components followed by assembly to make the final device. Structural and moving components, labile bio-molecules, fluids and temperature-sensitive materials place special restrictions on the bonding processes that can be used for assembly of MEMS devices. We describe a room temperature "stamp and stick (SAS)" transfer bonding technique for silicon, glass and nitride surfaces using a UV curable adhesive. Alternatively, poly(dimethylsiloxane) (PDMS) can also be used as the adhesive; this is particularly useful for bonding PDMS devices. A thin layer of adhesive is first spun on a flat wafer. This adhesive layer is then selectively transferred to the device chip from the wafer using a stamping process. The device chip can then be aligned and bonded to other chips/wafers. This bonding process is conformal and works even on surfaces with uneven topography. This aspect is especially relevant to microfluidics, where good sealing can be difficult to obtain with channels on uneven surfaces. Burst pressure tests suggest that wafer bonds using the UV curable adhesive could withstand pressures of 700 kPa (7 atmospheres); those with PDMS could withstand 200 to 700 kPa (2-7 atmospheres) depending on the geometry and configuration of the device.     

Etching processes for High Aspect Ratio Micro Systems Technology (HARMST)

 This paper reports on the development of a dry etching based HARMS-Technology which will offer the potential to manufacture micro-engines, micro-turbines, micro-sensors, micro-actuators, and electronic circuits onto a single silicon IC chip. This technology is based on the highly anisotropic and selective dry etching of Si-monocrystals. The suitability of reactive ion etching for the fabrication of micro electro mechanical systems (MEMS) has been evaluated by characterising the change of lateral dimensions vs. depth in etching deep structures in silicon. Fluorine, chlorine and bromine containing gases have provided the basis for this investigation. A conventional planar RIE (Reactive Ion Etching) reactor has been used, in some cases with magnetic field enhancement or ICP (Inductive Coupled Plasma) Source and low substrate temperature. For reactive ion etching based on Cl₂ or Cl₂/HBr plasma a slightly “positive” (top wider than bottom) slope is achieved when etching structures with a depth of several 10 μm, whereas a “negative” slope is obtained when etching with an SF₆/CCl₂F₂ based plasma. Pattern transfer with vertical walls is obtained for reactive ion etching based on SF₆ (with O₂ added) when maintaining the substrate at low temperature (in range ≈−100 °C). Further optimisation of plasma chemistries and reactive ion etching procedures should result in runouts in the order or 0.1 μm/100 μm depth in Si as well as in organic materials. Etching processes for HARMST is demonstrated in the realisation in Si microturbine. Axes or stators (nonmoving parts) are etched into the initial Si-wafer. The movable parts (rotors, beams, etc.) are prepared from electro-chemically etched Si-membranes with defined thicknesses that, all movable parts are created lithographically on the SiN_xO_y surface. This is followed by dry etching the mono-crystalline Si-membrane down to the SiN_xO_y sacrificial layer on the back side of the membrane by an RIE-process. The wafer with the movable parts is flipped onto the wafer with the already etched axis and then positioned and centred. The SiN_xO_y-sacrificial layer is then dissolved by a chemical wet or vapour etch process. Subsequent bonding with a Pyrex glass wafer seals the parts. Received: 30 October 1995/Accepted: 20 May 1996     

Research on forming and application of U-form glass micro-nanofluidic chip with long nanochannels

The forming process of U-form glass micro-nanofluidic chip with long nanochannels is presented in this paper, in which the fabrication of channels and the assembly of plates are included. The micro-nanofluidic chip is composed of two glass plates in which there are microchannels and nanochannels, respectively. This chip can be used for trace sample enrichment, molecule filtration, and sample separation, etc. In fabrication process, the two-step photolithograph on one wafer is often required in early papers, as nano and micro structure designed in one plate have different depths. In this paper, the channels in micro-nanofluidic chip are designed in two glass plates instead of in one wafer. The nanochannels and microchannels are, respectively, formed on plates using wet etching and two-step photolithograph on one wafer is not required. Since the channels are formed, the upper plate and the bottom plate are assembled together by alignment, preconnection and thermal bonding orderly. Firstly these plates are aligned with the cross-marks on an inverted microscope. The aqueous film between plates is controlled to decrease the static friction force for accurate adjustment. Then the adhesion strength of connection is enhanced with semi-dry status for limiting movement from slight inclining and shaking. At last, the bottom plate and the upper one are irreversibly linked together with thermal bonding. The heating period and max temperature of thermal bonding are optimized to eliminate thermal stress gradient and the size shrinking. With the micro-nanofluidic chip, the 1 μM fluorescein isothiocyanate in 10 mM PBS buffer is concentrated successfully. The sample concentrating factor of light intensity varies from 2.2 to 8.4 with applied voltages between 300 and 2,000 V. The switch effect and the instability effect in concentrating process are described and analyzed too.     

基于局部与非局部线性判别分析和高斯混合模型动态集成的晶圆表面缺陷探测与识别

在复杂的半导体制造过程中,晶圆生产经过薄膜沉积、蚀刻、抛光等多项复杂的工序,制造过程中的异常波动都可能导致晶圆缺陷产生.晶圆表面的缺陷模式通常反映了半导体制造过程的各种异常问题,生产线上通过探测和识别晶圆表面缺陷,可及时判断制造过程故障源并进行在线调整,降低晶圆成品率损失.本文提出了基于一种流形学习算法与高斯混合模型动态集成的晶圆表面缺陷在线探测与识别模型.首先该模型开发了一种新型流形学习算法——局部与非局部线性判别分析法(Local and nonlocal linear discriminant analysis, LNLDA),通过融合数据局部/非局部信息以及局部/非局部惩罚信息,有效地提取高维晶圆特征数据的内在流形结构信息,以最大化数据不同簇样本的低维映射距离,保持特征数据中相同簇的低维几何结构.针对线上晶圆缺陷产生的随机性和复杂性,该模型对每种晶圆缺陷模式构建相应的高斯混合模型(Gaussian mixture model, GMM),提出了基于高斯混合模型动态集成的晶圆缺陷在线探测与识别方法.本文提出的模型成功地应用到实际半导体制造过程的晶圆表面缺陷在线探测与识别,在WM-811K晶圆数据库的实验结果验证了该模型的有效性与实用性.     

Roll-to-roll hot embossing of microstructures

In this paper we present a new roll-to-roll embossing process allowing the replication of micro patterns with feature sizes down to 0.5 μm. The embossing process can be run in ‘continuous mode’ as well as in ‘discontinuous mode’. Continuous hot embossing is suitable for the continuous output of micro patterned structures. Discontinuous hot embossing has the advantage that it is not accompanied by waste produced during the initial hot embossing phase. This is because in ‘discontinuous mode’, embossing does not start before the foil has reached the target temperature. The foil rests between two parallel heating plates and foil movement and embossing starts only after the part of the foil resting between the heating plates has reached a thermal steady state. A new type of embossing master is used which is based on flexible silicon substrates. The embossing pattern with sub-μm topographic resolution is prepared on silicon wafers by state of the art lithography and dry etching techniques. The wafers are thinned down to a thickness of 40 μm, which guarantees the mechanical flexibility of the embossing masters. Up to 20 individual chips with a size of 20 × 20 mm2 were assembled on a roller. Embossing experiments with COC foils showed a good replication of the silicon master structures in the foil. The maximum depth of the embossed holes was about 70% of the master height.     

Study of residual stress-induced deformation of multilayer cantilever for maskless microplasma etching

In the scanning probe microscopy-based microplasma etching system proposed by our group, the microcantilever probe integrated with microplasma device is a multilayered structure. However, the thin film residual stress generated by microfabrication process may cause undesirable bending deformation of the cantilever. In order to predict and minimize the stress-induced deformation in the cantilever design, we experimentally measure and calculate each thin film stress of the cantilever based on Stoney equation. Then the stress-induced bending deformation of the cantilever is simulated by finite element simulation. By adjusting the thickness of reserved silicon layer of the cantilever, the deflection can be minimized to <5 μm for a 750 μm-length cantilever. Finally the microcantilever probes with different thickness of reserved silicon layer are successfully fabricated by MEMS process. The bending deformation of actual fabricated cantilevers agree well with simulation results, which verifies the feasibility of the cantilever structural design. The results of this paper may lay a foundation for further scanning plasma maskless etching.     

Mechanical and electrical bonding between silicon wafer and glass wafer with etched channels containing metal tracks

In this paper a novel process to bond and, at the same time, to electrically connect a silicon wafer to a glass wafer is presented. It consists of a low temperature anodic bonding process between silicon and glass by using a glass wafer with etched channels in order to contain metal tracks. The glass-to-silicon anodic bonding process at low temperatures (not exceeding 300°C) assures a strong mechanical link (Berthold et al. in Transducers 1999, June:7–10, 1999). The electrical contacts between the metal pads on the backside of a silicon wafer and the metal pads on the glass wafer are achieved by sintering and diffusion of metals due to a kind of thermo compression bonding. This bonding method permits a high vertical control due to a well-controlled etching of the cavity depth and to the thickness precision of both metallization (pads on silicon wafers and metal tracks on glass wafer). This IC-processing compatible approach opens up the way to a new electrical connection concept keeping, at the same time, a strong mechanical bond between glass and silicon wafers for an easier fabrication of a more complex micro-system.     

Study on three-dimensional micromachining using synchrotron radiation etching

 In this paper, we proposed a new approach of three-dimensional (3-D) micromachining without using any masks. This approach is a direct writing using synchrotron radiation (SR) etching. Several approaches to fabricate 3-D microstructures using photo-lithography have been proposed. However, these approaches are limited to fabricate microstructures due to the using mask process. SR etching is a dry process, and the etching rate of PTFE (polytetrafluoroethylene) is so high (100 μm/min) in vacuum using the SR white light. By utilizing a high processing speed and smoothness of the etched surfaces, SR etching might have a potential for 3-D micromachining by combining the direct writing with a stage having a high degree of freedom. Here, we reported the results of 3-D micromachining of PTFE using SR etching in vacuum and examined the dependence of SR etching of PTFE on the etching environment under an atmospheric pressure of He. Received: 10 August 2001/Accepted: 24 September 2001 This paper was presented at the Fourth International Workshop on High Aspect Ratio Microstructure Technology HARMST 2001 in June 2001.     

Micromachining of buried micro channels in silicon

A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the sidewalls of the trench, removal of the coating at the bottom of the trench, and etching into the bulk of the silicon substrate. The structures can be sealed by deposition of a suitable layer that closes the trench. BCT is a process that can be used to fabricate complete micro channels in a single wafer with only one lithographic mask and processing on one side of the wafer, without the need for assembly and bonding. The process leaves a substrate surface with little topography, which easily allows further processing, such as the integration of electronic circuits or solid-state sensors. The essential features of the technology, as well as design rules and feasible process schemes, will be demonstrated on examples from the field of μ-fluidics     

Fabrication methods based on wet etching process for the realization of silicon MEMS structures with new shapes

In this paper, fabrication methods are developed in order to realize the silicon microelectromechanical systems components with new shapes in {100} Si wafers. Fabrication process utilizes wet etching with a single step of photolithography. The silicon etching is carried out in complementary metal oxide semiconductor process compatible pure and surfactant Triton-X-100 [C₁₄H₂₂O(C₂H₄O] _n , n = 9–10) added tetramethylammonium hydroxide (TMAH) solutions. The fabricated structures are divided in two categories: fixed and freestanding. The fixed structures are realized in single oxidized silicon wafers, while freestanding are formed in silicon nitride-based silicon on insulator (SOI) wafers. The SOI wafers are prepared by bonding the oxidized and the nitride deposited wafers, followed by thinning and chemical mechanical polishing processes. The etching results such as {100} and {110}Si etch rates, undercutting at rounded concave and sharp convex corners and etched surface morphologies are measured in both pure and Triton added TMAH solutions. Different concentrations of TMAH are used to optimize the etching conditions for desired etched profiles.     

Design, fabrication and testing of a high performance silicon piezoresistive Z-axis accelerometer with proof mass-edge-aligned-flexures

This paper presents design, fabrication and testing of a quad beam silicon piezoresistive Z-axis accelerometer with very low cross-axis sensitivity. The accelerometer device proposed in the present work consists of a thick proof mass supported by four thin beams (also called as flexures) that are connected to an outer supporting rim. Cross-axis sensitivity in piezoresistive accelerometers is an important issue particularly for high performance applications. In the present study, low cross-axis sensitivity is achieved by improving the device stability by placing the four flexures in line with the proof mass edges. Various modules of a finite element method based software called CoventorWare^™ was used for design optimization. Based on the simulation results, a flexure thickness of 30 μm and a diffused resistor doping concentration of 5 × 10¹⁸ atoms/cm³ were fixed to achieve a high prime-axis sensitivity of 122 μV/Vg, low cross-axis sensitivity of 27 ppm and a relatively higher bandwidth of 2.89 kHz. The designed accelerometer was realized by a complementary metal oxide semiconductor compatible bulk micromachining process using a dual doped tetra methyl ammonium hydroxide etching solution. The fabricated accelerometer devices were tested up to 13 g static acceleration using a rate table. Test results of fabricated devices with 30 μm flexure thickness show an average prime axis sensitivity of 111 μV/Vg with very low cross-axis sensitivities of 0.652 and 0.688 μV/Vg along X-axis and Y-axis, respectively.     

Fabrication of an accurately vertical sidewall for optical switch applications using deep RIE and photoresist spray coating

The authors propose a new approach for fabricating an accurately vertical sidewall by deep RIE process for optical MEMS device applications. The etching area is divided in two patterns, an outline pattern and area pattern. The first pattern defines the outline of the etching area and has a uniform pattern width of 70–80 μm to achieve accurately vertical trench etching within 0.1°. The remaining area is removed by successive second etching using another pattern. The difficulties involved with multiple deep etchings are overcome by the combination of a photoresist spray coating and the side etching effect of RIE controlled by recipe control. The fabrication of mirror structure with 90.1° sidewall is demonstrated using the above procedures. Moreover, an inverted nickel mold is exhibited using electroplating. The resulting accurately vertical sidewall is considered to be effective for achieving lower insertion loss and easier optical alignment for MEMS optical devices.     

Tensile testing of microfabricated thin films

 Mechanical properties of titanium thin films of 0.5 μm thickness and aluminum thin films of 1.0 μm thickness, microfabricated by magnetron sputtering, were measured by using a novel tensile machine. These thin films are difficult to handle because they are fragile, so the thin film specimens were fabricated by using semiconductor manufacturing technology in a silicon frame to protect them. The test section of these specimens was 300 μm in width and 1400 μm in gauge length. By gripping the thin film specimen with a new device using a micrometer, it could be mounted on the tensile machine easily. The stress-strain diagrams of both thin films were measured continuously in the atmosphere at room temperature. The experimental results indicated that the titanium thin film and the aluminum thin film had a smaller breaking elongation although they had a larger tensile strength than bulk pure titanium and bulk pure aluminum, respectively. Received: 31.10.96/Accepted: 14.11.96     

Fabrication of compliant high aspect ratio silicon microelectrode arrays using micro-wire electrical discharge machining

This paper reports on the fabrication of high aspect ratio silicon microelectrode arrays by micro-wire electrical discharge machining (μ-WEDM). Arrays with 144 electrodes on a 400 μm pitch were machined on 6 and 10 mm thick p-type silicon wafers to a length of 5 and 9 mm, respectively. Machining parameters such as voltage and capacitance were varied for different wire types to maximize the machining rate and to obtain uniform electrodes. Finite element analysis was performed to investigate electrode shapes with reduced lateral rigidity. These compliant geometries were machined using μ-WEDM followed by a two step chemical etching process to remove the recast layer and to reduce the cross sections of the electrodes.