Sharing memory in banyan-based ATM switches

We study a multistage ATM switch in which shared-memory switching elements are arranged in a banyan topology. By “shared-memory,” we mean that each switching element uses output queueing and shares its local cell buffer memory among all its output ports. We apply a buffer management technique called delayed pushout that was originally designed for multistage ATM switches with hierarchical topologies. Delayed pushout combines a pushout mechanism, for sharing memory efficiently among queues within the same switching element, and a backpressure mechanism, for sharing memory across switch stages. The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a variety of traffic conditions. Of the five schemes we simulate, delayed pushout is the only one that performs well under all load conditions     

Distributed routing protocols for ATM extended Banyan networks

It is well known that a multistage banyan network, which is a single-path blocking structure, becomes rearrangeable nonblocking in a circuit-switching environment if the number of its stages is increased so as to obtain a Benes network. Banyan networks, provided with a shared queue in each switching element, have often been proposed as the core of an interconnection network for an ATM packet switching environment. In this scenario, if the classical interstage backpressure protocols are used, adding stages to a banyan network can even degrade the banyan network performance, in spite of the multipath capability given by the additional stages. A class of new simple interstage protocols is here defined to operate in the added stages of the banyan network so that a sort of sharing of the queueing capability in each added stage is accomplished. Large improvements in the traffic performance of these extended banyan networks are obtained, especially in the region of offered loads providing a low packet loss probability     

A new buffer management scheme for hierarchical shared memoryswitches

We study a multistage hierarchical asynchronous transfer mode (ATM) switch in which each switching element has its own local cell buffer memory that is shared among all its output ports. We propose a novel buffer management technique called delayed pushout that combines a pushout mechanism (for sharing memory efficiently among queues within the same switching element) and a backpressure mechanism (for sharing memory across switch stages). The backpressure component has a threshold to restrict the amount of sharing between stages. A synergy emerges when pushout, backpressure, and this threshold are all employed together. Using a computer simulation of the switch under symmetric but bursty traffic, we study delayed pushout as well as several simpler pushout and backpressure schemes under a wide range of loads. At every load level, we find that the delayed pushout scheme has a lower cell loss rate than its competitors. Finally, we show how delayed pushout can be extended to share buffer space between traffic classes with different space priorities     

宽带ISDN与ATM交换技术：第三讲 ATM交换技术

本文介绍了ＡＴＭ交换的基本原理，研究了ＡＴＭ交换结构的分类，并讨论了几种典型的ＡＴＭ交换网络，包括ＢＳＳ交换结构、Ｂｏｘａｎｎｅ交换单元和交换机构以及Ｂａｔｃｈｅｒ－Ｂａｎｙａｎ多级互连网络。     

Rerouting network: a high-performance self-routing switch forB-ISDN

A high-performance self-routing switch is proposed for ATM (asynchronous transfer mode) switch systems. Switching performance is enhanced by a rerouting algorithm applied to a particular multistage interconnection algorithm. The interconnection algorithm offers many access points to the output and resolves output contention by layering buffers at each switching stage. The author analyzes switching performance and shows that this switch can be easily engineered to have high throughput and low cell loss probability by increasing the number of switching stages. The author also illustrates that the number of switching stages required for a given cell loss probability shows gradual growth with increasing switch size. Analysis shows that the proposed switch is robust even with respect to nonuniform traffic     

An approximate model of a switching network carrying mixture ofdifferent multichannel traffic streams

An approximate model of a multistage switching network carrying a mixture of different multichannel traffic streams is proposed. In the model the multistage switching network is reduced to a single-channel system, that is, to an Erlang ideal grading to which a mixture of different multichannel traffic is offered. An approximate method for recurrence determination of the distribution of being busy in such grading is presented. The determined distribution enables calculation of blocking probabilities for traffic streams of various classes. The derived formula is a generalization of Kaufman (1981) and Robert's (1981) recurrence formula covering a full-availability trunk group with various multichannel traffic streams, and it can be useful for the analysis of ISDN systems     

ATM交换结构——多级互连网络

ATM交换结构是ATM交换的关键技术之一,而多级互连网络(MIN)以其优异特性在 ATM交换中得到广泛应用。本文介绍了 MIN 的分类、拓扑结构、缓冲策略和控制机理。     

自相似业务合成流的建模及排队性能分析

近期起初网络流量分析表明很多信息源会产生在多时间尺度下具有自相似特性的信息流,据此人们采用模拟及分析的方法对此种业务流对ＡＴＭ交换机／复用器性能的进行了研究,发现了与传统短打关模型完全不同的排除生但是到２为止对于自相关信息流的复用问题尚未发现有要进行研究。而这个问题的解决对自相似业务流条件下的ＡＴＭ交换机／复用器性能分析,接入控制（ＣＡＣ）等都具有很重要的意义。本文基于临界时间尺度的概念对这个问题     

Dimensioning an ATM switch based on a three-stage Clos interconnection network

ATM (asynchronous transfer mode) is a new technique for transmitting voice, data and video. The performance of atm networks will depend on switch structure. Performance analysis of an atm switch based on a three-stage Clos network is presented. In this paper two types of switches are studied: a switch with input queues in the switching elements and a switch with output queues. This study is at the cell level and intends to dimension the switch. First, the traffic is supposed to be uniform, cells arrive on each input according to a geometric arrival process, they are uniformly directed over all the network outputs. An analytic model is proposed for both input and output queues in the switching elements. A study of the saturation throughput is proposed for input buffer switching elements. This work proves the influence of buffer dimensioning on the different stages of the switch. Dissymmetric switching elements are shown to be better than symmetric ones. A model is then designed for nonuniform traffic patterns and output buffers. Two types of non-uniform traffic are presented: single source to single destination (sssd) and multi-hot spots traffic (mhs). Discrete event simulations are used to validate the different models.     

The deflection self-routing Banyan network: A large-scale ATMswitch using the fully adaptive self-routing and its performanceanalyses

Because the Internet traffic, that will be the major traffic of broadband integrated services digital networks, is bursty when cells are being switched within the multistage switching network, it has a higher possibility that multiple cells arriving simultaneously at a switching element through different incoming links may have to be forwarded along the same outgoing link. We propose a high-performance large-scale ATM switch dealing with such link contention problem. It is a new unbuffered augmented Banyan network using fully adaptive self-routing control: the deflection self-routing Banyan network. To utilize all the links of the network as alternate paths, we employ the deflection-routing algorithm in each switching element, such that cells failing to get selected for the intended link are sent along different links, in the hope that they later return, or detour the contended link and continue their journey to the destination. Cells are never dropped within the switching network, whereas the switch has no multiple cell buffers. The proposed routing is as simple as that of the generic Banyan network, and all the switch elements (SEs) have a uniform structure. To design the proposed network and its self-routing, we use the topological properties that all the SEs of the Banyan network are arranged in a regular pattern topologically. We formulate and prove these properties through an algebraic formalism. We also ran a performance analysis to provide quantitative comparison against the Banyan network and the replicated Banyan networks. As a result, we show that the new network has a far better performance and scalability than the other networks     

Designing a CORBA-based high performance open programmablesignaling system for ATM switching platforms

ATM switching platforms are well suited for transporting multimedia streams with quality-of-service (QOS) requirements. This paper describes the system design of a high performance connection management system for xbind, a flexible open programmable signaling system for ATM switching platforms. The latency and throughput of call processing is improved by caching, message aggregation, and processing of requests in parallel. Using a set of general purpose UNIX work stations, we are able to attain a maximum throughput of close to 600000 call operations/h (setup and delete) with an average call setup time of 85 ms. With a low traffic load of 3600 call operations/h, an average call setup latency of 11 ms can be obtained. The system is adaptive. By adjusting various control parameters, the connection manager(s) can be dynamically configured to trade off between throughput and call setup time     

Performance analysis of the ATM shuffleout switch under arbitrarynonuniform traffic patterns

Shuffleout is a blocking multistage asynchronous transfer mode (ATM) switch using shortest path routing with deflection, in which output queues are connected to all the stages. This paper describes a model for the performance evaluation of the shuffleout switch under arbitrary nonuniform traffic patterns. The analytical model that has been developed computes the load distribution on each interstage link by properly taking into account the switch inlet on which the packet has been received and the switch outlet the packet is addressing. Such a model allows the computation not only of the average load per stage but also its distribution over the different links belonging to the interstage pattern for each switch input/output pair. Different classes of nonuniform traffic patterns have been identified and for each of them the traffic performance of the switch is evaluated by thus emphasizing the evaluation of the network unfairness     

Performance analysis of ATM banyan networks with shared queueing.II. Correlated/unbalanced offered traffic

For pt.I see ibid., vol.2, no.4, p.398-410 (1994). The paper develops the analysis of multistage banyan interconnection networks in which the switching elements are provided with a buffer shared among all the inlets and outlets of the element. Two different internal protocols are considered for the transfer of packets from stage to stage based on the presence or absence of interstage backpressure to signal the occurrence of buffer saturation conditions. The analytical model is based on the representation of the switching element state by means of only two variables. Two kinds of offered traffic patterns are considered, a bursty balanced pattern and an unbalanced uncorrelated pattern. In this latter case, the load above the average is supposed to be addressed either to a single network outlet, or to a given group of network outlets     

Management and control functions in ATM switching systems

As research has progressed, it has become clear that the main difficulties in ATM pertain to its operational details rather than the concept. And it seems likely that these control issues will be much more complicated and costly for ATM switches when compared with current telephone circuit switches. The asynchronous transfer mode (ATM) is the target switching technique for the future public broadband integrated services digital network (B-ISDN). The purpose of this article is to examine the management and control functions in ATM switching systems implied by current industry standards and agreements on OAM and traffic control. Until now, ATM research in the areas of switch design and traffic control have progressed essentially independently. First, we briefly review the B-ISDN Protocol Reference Model and its representation of the different information flows in ATM. Network management and traffic control principles in ATM, and in particular OAM, are overviewed. With this information as background, we attempt to infer their implications on the functional blocks of an ATM switching system. An example switch architecture model with distributed management and control functions is outlined, and some design issues are discussed     

MULTICAST ROUTING SCHEMES IN ATM

In this study, we investigate the problem of accommodating multicast traffic in ATM networks, with emphasis on the virtual path (VP) environment. We propose a network structure called “virtual copy network” that is suitable for multicast communication and connection setup scheme, taking into account the VP environment. With our technique, we can expect statistical multiplexing gain in accommodating multiple multicast traffic streams over a VP. Also, we propose two multicast routing algorithms (the CNR-LH algorithm and the improved CNR-LH algorithm) for an ATM network environment. In these algorithms, in addition to determining an adequate route, the exact corresponding VPs on the route are also obtained. We examine the efficiency of the algorithms by demonstrating their basic characteristics using computer simulations.     

PERFORMANCE ANALYSIS FOR ATM SWITCHING OF MIXED CONTINUOUS-BIT-RATE AND BURSTY TRAFFIC WITH SMOOTHING FUNCTION

Traditional packet switching networks have typically employed window-based congestion control schemes in order to regulate traffic flow. In ATM networks, the high speed of the communication links and the varied nature of the carried traffic make such schemes inappropriate. Therefore, simpler and more efficient schemes have to be proposed to improve the congestion control for ATM switching. This paper presents an exact performance analysis of ATM switching whose inputs consist of Continuous-Bit-Rate(CBR) and bursty traffic. The CBR traffic and bursty traffic are described by Bernoulli process and the Interrupted Bernoulli Process(IBP), respectively. Bursty traffic smoothing mechanism is analyzed. With the use of a recursive algorithm, the cell loss probability and the average delay for ATM switching of mixed CBR and bursty traffic are exactly calculated. Traffic smoothing could be implemented at a slower peak rate keeping the average rate constant or decreasing the average bursty length. Both numerical a     

Reliability of multistage production systems controlled byautomated visual inspection

A probability model that examines the reliability of a failure-prone multistage production process controlled by a mechanism consisting of multiple cameras (one for each stage) and a single processor which is shared among all the stages (one stage at a time) is presented. The control functions for each stage and the system characteristics are presented. A computational formula for the steady-state reliability of such a production process is developed. The steps in the computation are for a specific system which serves as a numerical example. Model applications include performance evaluation of automated control mechanisms under various combinations of system parameter values and switching schedules     

Optimal queueing discipline for real-time traffic at ATM switchingnodes

Queueing disciplines at asynchronous transfer mode (ATM) switching nodes handling various kinds of real-time traffic are investigated. ATM can support various new services including voice, data, and video. However, the characteristics of superposed traffic carried by ATM are not known, and a control effective for a versatile arrival process is required. The optimal discipline which minimizes the number of cells being delayed beyond the specified maximum allowable time, and thus being discarded is derived, without assumptions on the arrival process of cells and buffer management schemes. Also discussed is implementation of the optimal discipline and a method of satisfying cell loss probability requirements of individual classes     

Evaluating the limit behavior of the ATM traffic within a network

This paper is concerned with the ATM traffic characterization within the network. Most of the work performed up to now has studied the effects of traffic on the access multiplexer and the first switch of an ATM network. Various source models were assumed to generate the ATM traffic. So, while the performance of a single switch node has been exhaustively examined, the statistical behavior of the traffic modified as it crosses the network has not been thoroughly analyzed yet. This paper, through an analysis of a network of cascaded queues, indicates that limit distributions exist in the statistical behavior of the traffic streams and in the queue performance, although a formal proof is believed to be very hard to obtain. The first modelling step consists of deriving the exact interdeparture time distribution for the cells of a reference-connection arriving to the output queue of a switch node with a general interarrival time distribution and multiplexed with a background traffic stream. The analysis is iterated through a long sequence of cascaded output queues, until the interdeparture time distribution converges. Simulations show that the analytical results are accurate at each stage of the network under the hypothesis of independent queues, and are also good approximations in the case of correlated queues. This study shows that the queue performance at the limit point is always better than the M/D/1 case. The distributions found in this way depend only on the connection bandwidth and on the background traffic behavior. The initial characteristics of a connection (burst length distributions and burst interarrival time distributions) only influence the convergence speed, not the limit distribution     

Optimal cost/performance design of ATM switches

This paper proposes a methodology for performing an evaluation and optimization of the cost of an ATM switching architecture under performance constraints given in terms of virtual connection blocking probability. An analysis of blocking networks is developed, and combined with known results concerning nonblocking networks, provides a theoretical model which relates traffic characteristics, network topology and blocking probability in a multirate/multiservice broadband environment. An analysis of the characteristics determining the cost of a generic ATM switch implementation follows. The model is oriented to optimize both the topological parameters and the speed advantage, with respect to the main cost factors of VLSI-based switching networks i.e., components count and complexity, interconnection costs