A sub-10-ns 16/spl times/16 multiplier using 0.6-/spl mu/m CMOS technology

A 16/spl times/16-b parallel multiplier fabricated in a 0.6-/spl mu/m CMOS technology is described. The chip uses a modified array scheme incorporated with a Booth's algorithm to reduce the number of adding stages of partial products. The combination of scaled 0.6-/spl mu/m CMOS technology and advanced arithmetic architecture achieves a multiplication time of 7.4 ns while dissipating only 400 mW. This multiplication time is shorter than other MOS high-speed multipliers previously reported and is comparable to those for advanced bipolar and GaAs multipliers.     

A high-speed LSI GaAs 8/spl times/8 bit parallel multiplier

Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed. The largest of these circuits, an 8/spl times/8 bit multiplier, has 1008 gates, and is by far the most complex GaAs IC demonstrated today. This multiplier forms the 16 bit product of two 8 bit input numbers in 5.25 ns. This corresponds to an equivalent gate propagation delay of 150 ps/gate. The power dissipation ranges between 0.6-2 mW/gate.     

25-ns 256K/spl times/1/64K/spl times/4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.     

A low-power, bipolar, two's complement serial pipeline multiplier chip

A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (3) 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) overflow corrector. Packages can be cascaded to provide functions of length greater than 4 bits. Nonsaturating circuit techniques, emitter function logic combined with current-steering trees, are effectively utilized to make high-performance, low-power circuits using a simple bipolar technology. The multiplier circuitry is compatible at inputs and outputs with standard emitter coupled logic and uses a standard -5.2/spl plusmn/10 percent power supply. Fully programmable multiplication at clock rates greater than 20 MHz is achieved with a power consumption of 37.5 mW/bit.     

A 7-ns/850-mW GaAs 4-kb SRAM with little dependence on temperature

A GaAs 1 K×4-kb SRAM designed using a novel circuit technology is described. To reduce the temperature dependence and the scattering of the access time, it was necessary to increase the signal voltage swing and to reduce the leakage current in access transistors of unselected memory cells. In the 4-kb SRAM, source-follower circuits were adopted to increase the voltage swing, and the storage nodes of unselected memory cells were raised by about 0.6 V to reduce the subthreshold leakage current in the access transistors. The 4-kb SRAM was fabricated using 1.0-μm self-aligned MESFETs with buried p-layers beneath the FET regions. A maximum address access time of 7 ns and a power dissipation of 850 mW were obtained for the galloping test pattern at 75°C. Little change in the address access time was observed between 0 and 75°C     

A 70-MHz 8-bit/spl times/8-bit parallel pipelined multiplier in 2.5-/spl mu/m CMOS

A design is presented for an 8-bit/spl times/8-bit parallel pipelined multiplier for high speed digital signal-processing applications. The multiplier is pipelined at the bit level. The first version of this multiplier has been fabricated in 2.5-/spl mu/m CMOS technology. It has been tested at multiplication rates up to 70 MHz with a power dissipation of less than 250 mW. Clock skew, a major problem encountered in high-speed pipelined architectures, is overcome by the use of a balanced clock distribution network all on metal, and by proper use of clock buffers. These issues and the timing simulation of the pipeline design are discussed in detail. Possible extensions and improvements for achieving higher performance levels are discussed. The conversion of the two-phase clocking scheme to an inherently single-phase clock approach is one possible improvement. A design using this approach has been simulated at 75 MHz and is currently being fabricated.     

A 35-ns 128K/spl times/8 CMOS SRAM

A 128 K/spl times/8-b CMOS SRAM with TTL input/output levels and a typical address access time of 35 ns is described. A novel data transfer circuit with dual threshold level is utilized to obtain improved noise immunity. A divided-word-line architecture and an automatic power reduction function are utilized to achieve a low operational power of 10 mW at 1 MHz, and 100 mW at 10 MHz. A novel fabrication technology, including improved LOCOS and highly stable polysilicon loads, was introduced to achieve a compact memory cell which measures 6.4/spl times/11.5 /spl mu/m/SUP 2/. Typical standby current is 2 /spl mu/A. The RAM was fabricated with 1.0-/spl mu/m design rules, double-level polysilicon, and double-level aluminum CMOS technology. The chip size of the RAM is 8/spl times/13.65 mm/SUP 2/.     

A 4-bit/spl times/4-bit multiplier and 3-bit counter in Josephson threshold logic

A fast Josephson circuit using a threshold logic is developed for application to a multiplier and a binary counter. The former is a typical combinational circuit and the latter is a typical sequential circuit. The junction and barrier materials used were Nb-AlO/SUB X/-Nb. An optimized asymmetric two-junction interferometer maximized the operating margin of the threshold gate. A speed-up junction was introduced to decrease the switching delay without sacrificing the operating margin. A dumping resistor, which was inserted parallel to the input signal line of the threshold gate between its two terminals, decreased the reflection of the input signal caused by the gate inductance, thereby ensuring the margin and speed. To demonstrate the high-speed possibility of the Josephson threshold logic, a high-speed experiment for the circuits was performed. The multiplier demonstrated 210-ps operation.     

A 16 bit/spl times/16 bit pipelined multiplier macrocell

A 16 bit/spl times/16 bit pipelined multiplier implemented in a two-layer metal 1.5 /spl mu/m CMOS/BULK technology has been developed. The design is based on the well-known modified Booth algorithm and is capable of operating at a 25 MHz clock rate. The multiplier is designed to be used as a macrofunction within larger chip designs. A structured design approach has been utilized so that reconfiguration of the basic array can be performed. The multiplier macrocell measures 1.7 mm/spl times/1.7 mm.     

A 200-mW GaAs 1 K SRAM with 2-ns cycle time

A very high-speed and low-power 1024/spl times/1 SRAM has been designed and fabricated using a normally-off recessed-gate FET technology. Minimum gate length is 0.7 /spl mu/m. A minimum access time of 1.4 ns has been obtained with a power dissipation of 210 mW. The memory cell area is 1197 /spl mu/m/SUP 2/ and the chip size is 1.91/spl times/2.21 mm/SUP 2/. The output voltage swing across a 50-/spl Omega/ load is 700 mV. The maximum simulated yield for 1 K SRAMs is discussed theoretically. A mean standard deviation in threshold voltage less than 15 mV is required to obtain 100% design yield. The SRAM has been shown to be fully operational using the march and checkerboard tests and exhibits read and write cycle times of 2 ns.     

A 40-ns/100-pF low power full-CMOS 256 K (32 K/spl times/8) SRAM

A fast and low-power full-CMOS 256 K (32 K/spl times/8-b) static RAM is described. Typical access time is 40 ns with a 100-pF load. Power dissipation is 100 mW at 10 MHz and <1 /spl mu/W in standby mode. The low standby power has been achieved by introducing a novel six-transistor, polysilicon-interconnected, double-cross-coupled cell. A novel output buffer design, a data-transition detection (DTD) circuit, and several other circuit techniques are introduced to obtain the speed and low active power dissipation. This chip is made in a 1.3-/spl mu/m, twin-tub, single-poly, double-metal technology with a p epi layer on p/SUP +/ substrate.     

A high-speed high-density silicon 8/spl times/8-bit parallel multiplier

An 8/spl times/8-bit parallel multiplier with submicrometer gate lengths has been fabricated using silicon NMOS technology. The multiplication time is 9.5 ns. This corresponds to an average loaded gate delay in the multiplier circuit of 244 ps/gate, which the authors believe is the shortest gate delay for MOS multiplier circuits demonstrated to date. The power dissipation is 600 mW at a supply voltage of 5 V. The multiplier circuit has a total of 1427 transistors in an active area of 0.61/spl times/0.58 mm/SUP 2/, corresponding to a gate density of 1125 gates/mm/SUP 2/.     

New radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithms for 3-D DFT

In this paper, new three-dimensional (3-D) radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) and radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) decimation-in-frequency (DIF) fast Fourier transform (FFT) algorithms are developed and their implementation schemes discussed. The algorithms are developed by introducing the radix-2/4 and radix-2/8 approaches in the computation of the 3-D DFT using the Kronecker product and appropriate index mappings. The butterflies of the proposed algorithms are characterized by simple closed-form expressions facilitating easy software or hardware implementations of the algorithms. Comparisons between the proposed algorithms and the existing 3-D radix-(2/spl times/2/spl times/2) FFT algorithm are carried out showing that significant savings in terms of the number of arithmetic operations, data transfers, and twiddle factor evaluations or accesses to the lookup table can be achieved using the radix-(2/spl times/2/spl times/2)/(4/spl times/4/spl times/4) DIF FFT algorithm over the radix-(2/spl times/2/spl times/2) FFT algorithm. It is also established that further savings can be achieved by using the radix-(2/spl times/2/spl times/2)/(8/spl times/8/spl times/8) DIF FFT algorithm.     

A 100-MHz 4-mW four-quadrant BiCMOS analog multiplier

A four-quadrant analog multiplier based on a simple, very linear, and fast BiCMOS transconductor using MOS transistors operating in the triode region and NPN bipolar devices is presented. The four quadrant operation is obtained by crosscoupling-in a Gilbert-cell fashion-two transconductors with a third stage used to modulate the transconductances of the former two. A chip prototype of the multiplier has been integrated in a 1.2-μm BiCMOS process to validate the idea. It has been designed to achieve high linearity on both inputs: measured results show a total harmonic distortion (THD) of less than -40 dB with a 3-V peak-to-peak input signal at 5 MHz from a 5-V supply and an output -3 dB bandwidth of 100 MHz while dissipating 4 mW from a 3-V supply. The integrated chip prototype active area is 1 mm²     

1/spl times/2 and 1/spl times/4 electrooptic switches

We describe the design, fabrication, and testing of two packaged electrooptic switches built from poled LiTaO/sub 3/ crystals. The 1/spl times/2 switch requires a driving voltage of 1200 V and exhibits insertion loss of 2.4 dB and crosstalk of -39.2 dB; the 1/spl times/4 switch exhibits insertion loss and crosstalk of 2.8 dB and -40.6 dB, respectively, and operates using a 1100-V voltage source. The maximum deflection time between the channels is 86 ns.     

2.5-mW single-mode operation of 1.55-/spl mu/m buried tunnel junction VCSELs

We present 1.55-/spl mu/m wavelength buried tunnel junction InGaAlAs-InP vertical-cavity surface-emitting lasers with low threshold current and high efficiency. An improved mirror design is accomplished with high-reflective low-loss epitaxial InGaAlAs-InAlAs and hybrid dielectric CaF/sub 2/-ZnS-Au layer stacks, respectively. Lasers with aperture diameters of only around 5 /spl mu/m exhibit continuous-wave single-mode output powers at room temperature well beyond 2 mW. Threshold voltages and series resistances as low as 0.9 V and 30-40 /spl Omega/ have been measured. The spectral behavior shows excellent performance over the relevant current and temperature range.     

A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-/spl mu/m CMOS process

A 1-V low-power high-speed dynamic-loading frequency divider is proposed using novel D flip-flops with a common-gate topology and with a single clock phase. A simple and accurate small-signal analysis model is provided to estimate the operating frequencies of the divider. Implemented in a standard digital 0.35-/spl mu/m CMOS process and at 1-V supply, the proposed frequency divider measures a maximum operating frequency up to 5.2 GHz with a power consumption of 2.5 mW.     

A 1.76-GHz 22.6-mW /spl Delta//spl Sigma/ fractional-n frequency synthesizer

A /spl Delta//spl Sigma/ fractional-N frequency synthesizer for the 2-GHz-range wireless communication applications is implemented in a 0.35-/spl mu/m BiCMOS process, using only CMOS components. The synthesizer achieves a close-in phase noise of -81 dBc/Hz, while the spurious tones are at -85 dBc. The synthesizer features a multiple-modulus prescaler employing the phase-switching architecture to minimize the power dissipation. The entire prescaler, including the gigahertz-speed first stages, is implemented using full-swing logic. The current source structure employed in the charge pump provides a constant output current over a wide, almost rail-to-rail output voltage range. The power dissipation of the synthesizer chip is 22.6 mW from a 2.7-V supply.     

A 21-ns 32 K/spl times/8 CMOS static RAM with a selectively pumped p-well array

The design and performance of a 32 K/spl times/8-b CMOS static RAM (SRAM) are presented. The design features a selectively pumped p-well array. Using this array technology, high-impedance polysilicon resistor loads can be used to reduce the array standby current by three orders of magnitude, and the device characteristics can be optimized to achieve high speed in the peripheral circuits. A unique divided-word-line architecture with shared sense amplifiers is used to achieve high-speed read operation. The read speed is further enhanced by a novel quasistatic equalization that minimizes peak current. A high-speed write circuit with a write-to-read transition detection is used to achieve a fast write operation. An advanced 1.2-/spl mu/m double-level-metal CMOS technology was used to fabricate the devices. The access time is 21 ns and the active power is 330 mW at 22 MHz.