CMOS switched-current ladder filters

The design and implementation of switched-current (SI) ladder filters is described. The basic current-mode circuits, including the SI differential integrator/summer are developed. The SI integrator/summer is shown to be directly analogous to the switched-capacitor (SC) integrator/summer; thus, all the synthesis techniques developed for the design of SC filters can be used to synthesize SI filters. Signal flowgraph synthesis of SI ladder filters is presented. The nonideal characteristics of SI ladder filters that limit their accuracy are evaluated. Clock-feedthrough and device mismatch induced errors are more severe in the present SI circuit configurations than in SC circuits. A standard digital 2-μm n-well CMOS process has been used to implement two high-order ladder filters. Simulations accurately predict the measured results of the first integrated SI filters. The area and power dissipation are comparable to those obtained with the switched-capacitor technique     

Offset- and gain-compensated and mismatch-free SC delay circuitwith flexible implementation

A novel SC delay circuit is presented that is insensitive to the DC offset and finite gain errors of operational amplifiers (OAs) as well as the capacitance ratio mismatch. The effectiveness is illustrated and consolidated by computer simulations. A comparison with typical compensated and uncompensated circuits in terms of magnitude, phase and offset errors is also presented. The circuit is also further extended to realise a wideband and very accurate successive-anticipatory gain compensation scheme and to flexibly implement arbitrary delay with only one OA     

Switched-capacitor interpolators without the input sample-and-holdfiltering effect

The authors propose new switched-capacitor (SC) interpolators whose frequency responses are no longer affected by the input sample-and-hold filtering effect which occurred in previous circuits. Two different types of architectures are discussed, one for input sampled-and-hold signals, and the other for arbitrary input signal formats. Examples are given to illustrate both types of SC interpolator circuits     

开关电容积分器的瞬态行为模型

对电路进行行为级模拟的关键是建立电子子模块的行为模型，用以描述电路模块的功能以及电路非理想效应的影响。本文采用瞬态分析方法，建立了基本模拟单元电路开关电容积分 的行为模型。由于对积分器中的运算放大器采用了单极点跨导运放模型，考虑了其有限增益、带宽、转换速率和输出阻抗的影响，提高了开关电容积分器行为模型的精度。电路模拟的结果表明，模型的误差在３％以内。     

单一单位增益放大器的Q增强SC滤波器

本文阐述了采用单位增益放大器的SC滤波器的设计方法。基于无源Q增强技术,由Sallew Key有源RC电路导出了一系列Q增强的二阶SC低通、高通和带通滤波器。设计表明,本文提出的Q增强SC电路比文献给出的电路需要小得多的电容分散度。本文考察了这些电路灵敏度和有限GB对SC电路的影响。用分立元件做了实验,实验结果与理论计算相吻合。     

Design of improved rail-to-rail low-distortion and low-stress switches in advanced CMOS technologies

This paper describes the efficient design of an improved and dedicated switched-capacitor (SC) circuit capable of linearizing CMOS switches to allow SC circuits to reach low distortion levels. The described circuit (SC linearization control circuit, SLC) has the advantage over conventional clock-bootstrapping circuits of exhibiting low-stress, since large gate voltages are avoided. This paper presents exhaustive corner simulation results of a SC sample-and-hold (S/H) circuit which employs the proposed and optimized circuits, together with the experimental evaluation of a complete 10-bit ADC utilizing the referred S/H circuit. These results show that the SLC circuits can reduce distortion and increase dynamic linearity above 12 bits for wide input signal bandwidths.     

HIGH SELECTIVITY SC BANDPASS FILTERS WITH LESS CAPACITOR SPREAD

Two novel switched-capacitor(SC)bandpass filters using a single operational am-plifier(op amp)are presented.Optimal designs for minimizing capacitor spread are also given.Gain-bandwidth product(GB)effects of op amps on the proposed SC circuits are taken intoconsideration.Comparisons with the proposed circuits and the circuits given by the literatureshow that the new circuits require less chip area in monolithic integration and are less sensitiveto the GB effects.     

Pseudo-N-path switched capacitor filters with out-of-band noise peaks

Novel pseudo-N-path (PNP) switched-capacitor (SC) integrator structures which avoid noise peaks in the main passband are described. They combine the simplicity of the previously proposed RAM-type PNP SC circuits with the desirable properties of hybrid-type circuits. Simulation results are presented for filters employing these structures to verify their usefulness.<>     

Implementation of switched capacitor fractional order differentiator (PDδ) circuit

This paper proposes a novel implementation of switched capacitor (SC) fractional order differentiators (FOD) based on Tustin operator and Al-Alaoui operator. The existing models of half differentiator s ^1/2 have been expanded using continued fraction expansion and implemented using PSpice. The PSpice simulation results are compared with the theoretical results in the continuous time domain. The results validate the effectiveness of the SC circuit implementation of the proposed approach. A detailed analysis of the influence of the non-idealities of the third order Al-Alaoui operator based half differentiator is performed. The analytical expressions for errors in magnitude and phase due to the above mentioned non-idealities have been derived for the SC integrator and amplifier circuits used in our realisation.     

SC amplifier and SC integrator with an accurate gain of 2

A fully differential switched-capacitor (SC) amplifier and integrator with an accurate gain of 2 are proposed. Both circuits are based on a novel capacitor mismatch compensation scheme which uses the same capacitor as the charge sampling and summing element. Therefore, the gain error which is linearly proportional to the capacitor mismatch in conventional SC circuits becomes proportional to the square of the mismatch. In addition, the proposed scheme does not require additional active blocks, and the valid output is generated within two clock cycles.     

一个开关电容电路的模拟和优化程序

本文介绍了一个以分析开关电容(SC)电路为目的面向用户的通用程序。该程序可以完成对SC电路的时域、频域和灵敏度模拟,可以对SC电路进行多目标优化,并可以求得SC电路的传输极点,且对电路的输入信号、开关序列、网络拓扑没有限制,文中提出了在改进节点法基础上求出电路传输极点的方法,以贡献的方式建立求传输函数对电容比的灵敏度方程,通过线性变换求得对电容比的灵敏度的方法和SC电路的多目标优化方法。最后给出了用该程序对SC电路进行模拟和优化的两个算例。     

Simple technique for analysis of SC networks using general-purpose circuit simulation programs

A new technique is proposed which enables the transformation of a large class of switched-capacitor (SC) networks into equivalent time-continuous (analogue) circuits to analyse them by use of standard, general-purpose circuit simulation programs such as SPICE It is based on a block partitioning, i.e. a total SC network is divided into small building blocks. It is shown how basic SC building blocks like integrators and summers can be modelled by equivalent two-ports containing only resistors, lossless transmission lines and current-controlled voltage sources. Furthermore, some new offset-free SC integrator schemes based on multi-step integration algorithms are also described.     

Sigma-delta modulator modeling analysis and design

This paper introduces a new method for SC sigma-delta modulator modeling.It studies the integrator's different equivalent circuits in the integrating and sampling phases.This model uses the OP-AMP input pair's tail current(I_0) and overdrive voltage(v_(on)) as variables.The modulator's static and dynamic errors are analyzed.A group of optimized I_0 and v_(on) for maximum SNR and power x area ratio can be obtained through this model.As examples, a MASH21 modulator for digital audio and a second order modu...     

A new simple method for analysing of thermal noise in switched-capacitor filters

Thermal noise is one of the most important challenges in analogue integrated circuits design. This problem is more crucial in switched-capacitor (SC) filters due to the aliasing effect of wide-band thermal noise. In this article, a new simple method is proposed for estimating the power spectrum density of output thermal noise in SC filters, which have acceptable accuracy and short running time. In the proposed method, first using HSPICE simulator, accurate value of accumulated sampled noise on sampler capacitors in each clock state is achieved. Next, using difference equations of the SC filter, frequency response of the SC filter is shaped by time domain analysis. Based on the proposed method, a SC low-pass filter and a second-order SC band-pass filter are analysed. The results are validated by comparing to the previously measured data.     

Polynomial Behavioural Modelling of Switched Capacitor Amplifiers

A data-based modeling technique for amplifiers in switched capacitor circuits is presented. The measured output settling error of a switched capacitor (SC) amplifier is presented as a two-dimensional polynomial of the initial voltages in the input and output nodes of the amplifier. This fitted polynomial can then be used as a very compact behavioral discrete-time model that can replicate also the output-dependent errors of the amplifier. The procedure is illustrated by characterizing an existing amplifier and using the fitted error model of it in behavioral simulations of a pipeline A/D converter.     

On the relationship between PSRR and clock feedthrough in SCfilters

A novel linearized model for calculating the power supply rejection ratio (PSRR) of switched-capacitor (SC) circuits due to switch charge injection (clock feedthrough) is presented. The inclusion of clock feedthrough accounts for the low-frequency PSRR degradation not modeled by other methods. This is particularly important in high-frequency SC circuits, as is confirmed by simulation and measurement results. The model defines a useful link between transient clock feedthrough analysis and effective coupling capacitor models that are suited for AC analysis. The abstraction of differentiating an injected charge with respect to voltage to get effective coupling capacitors leads to efficient analysis techniques, since clock delays and elaborate device models can be considered once at the outset, and then dispensed with in favor of simpler device elements. This makes the model more suitable for hand calculations and analysis with standard SC simulation packages     

开关电流电路及其误差分析

开关电流(SI)技术是有望取代开关电容技术的一种新的采样数据技术。首先介绍了开关电流技术的概念及优点,然后以SI电路基本存储单元为例分析了开关电流电路中可能存在的误差。最后,针对电路中存在的失配误差、传输误差、噪声误差及电荷注入误差等提出了一些解决方法,如S2I技术等。     

Switched-current circuit design issues

Switched-current (SI) circuits represent a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. Unlike switched-capacitor (SC) circuits, SI circuits require only a standard digital CMOS process. SI circuits use MOS transistors as the storage elements to provide analog memory capability. Similar to the operation of dynamic logic circuits, a voltage is sampled onto the gate of a MOSFET and held on its noncritical gate capacitance. The held voltage signal on the gate causes a corresponding held current signal in the drain, usually proportional to the square of the gate-to-source voltage. Design issues related to the implementation and performance of SI circuits are presented. SI filters show comparable performance to SC filters except in terms of passband accuracy. The major source of error is nonunity current gain in the SI integrator due to device mismatch and clock-feedthrough effects. For the initial CMOS prototypes, the current track and hold (T/H) gain error was about 2.5%