Discrete Lattice Wavelet Transform

The discrete wavelet transform (DWT) has gained a wide acceptance in denoising and compression coding of images and signals. In this work we introduce a discrete lattice wavelet transform (DLWT). In the analysis part, the lattice structure contains two parallel transmission channels, which exchange information via two crossed lattice filters. For the synthesis part we show that the similar lattice structure yields a perfect reconstruction (PR) property. The PR condition can be used to design half-band filters, which effectively eliminate aliasing in decimated tree structured wavelet transform. The DLWT can be implemented directly to any of the existing DWT algorithms     

Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme

Novel decomposed lifting scheme (DLS) is presented to perform one-dimensional (1D) discrete wavelet transform (DWT) with consistent data flow in both row and column dimension. Based on the proposed DLS, intermediate data can be transferred seamlessly between the column processor and the row processor in the hardware implementation of two-dimensional (2D) DWT, resulting in the reduction of on-chip memory, output latency and control complexity. Moreover, the implementation of 2D DWT can be easily extended to achieve higher processing speed with controlled increase of hardware cost. Memory-efficient and high-speed architectures are proposed to implement 2D DWT for JPEG2000, which are called fast architecture (FA) and high-speed architecture (HA). FA and HA can perform 2D DWT in N ² /2 and N ² /4 clock cycles for an N×N image, respectively, but the required internal memory is only 4N for 9/7 DWT and 2N for 5/3 DWT. Compared with the works reported in previous literature, the proposed designs provide excellent performance in hardware cost, control complexity, output latency and computing time. The proposed designs were implemented to process 2D 9/7 DWT in SMIC 0.18 μm CMOS logic fabrication with 4 KB internal memory for the image size 512 × 512. The areas are only 999137 um ² and 1333054 um ² for FA and HA, respectively, but the operation frequency can be up to 150 MHz.     

Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

一维离散小波变换的VLSI设计

文章提出了一种离散小波变换的VLSI结构。这种结构由四部分构成：输入延迟单元、寄存器单元、滤波器单元和控制单元。该结构采用了递归金字塔算法(RPA)取代传统的PA算法。只用一组滤波器即可完成所有级别的小波运算。同时，结合Short-Length FIR技术，以减少乘法和加法的运算次数。在寄存器单元的设计上，采用了Lifetime Analysis技术，结合Forward-Backward Register Allocation(FBRA)方法，使寄存器的数目降至最低。     

适于PCT编码的低内存离散小波变换

 基于常用的双正交对称DWT滤波器组的紧支撑性给出了一种适于基于PCT(Parent-Children Tree)的图像编码的低内存DWT实现方法—Stripe-Based DWT(SBWT).该方法生成与全局DWT相同的子带系数,且内存需求仅依赖于图像宽度、DWT滤波器组及分解层数.SBWT直接生成PCT,基于PCT的图像编码器与SBWT之间无需中间缓存.当采用CDF 9/7小波及5层分解时,相对于LBWT及Memory-constrained WT,SBWT的系统时延减小了31行,内存需求分别减小了18.4%与17.9%.     

基于离散插值样条的提升小波变换

文中引入了一种对信号递归滤波的提升方法,该方法与通常的提升方法不同之处是使用IIR滤波器.探讨了空间域中基于离散插值样条的预测算子和更新算子的设计.提出的方法以插值为基础,只涉及信号的采样,不要求使用正交公式,更适合信号的处理.最后由数值仿真验证了该算法的性能,对于软阈值法小波系数去噪,提升小波变换T12同B9/7相比,前者略优于后者,提升方法的优点在于其设计上的灵活性和计算花费少.     

离散小波变换的VLSI实现

离散小波变换已广泛应用于信号处理中。然而,实时小波变换需要大量运算,因此,专用小波变换芯片的设计已成为信号处理中的关键技术。文章提出了一种小波变换递归金字塔算法的VLSI结构,采用一组输入延迟单元和一个控制单元,用一组并行滤波器完成了小波变换。编写了相应的Verilog HDL模块,并进行了仿真和逻辑综合。     

A Higher Density Discrete Wavelet Transform

This paper describes a new set of dyadic wavelet frames with two generators. The construction is simple, yet the wavelets cover the time–frequency plane in an arrangement that provides a higher sampling in both time and frequency. Specifically, the spectrum of the first wavelet is concentrated halfway between the spectrum of the second wavelet and the spectrum of its dilated version. In addition, the second wavelet is translated by half integers rather than whole integers in the frame construction. This arrangement leads to an expansive wavelet transform that is approximately shift invariant and has intermediate scales. The wavelet frames presented in this paper are compactly supported and have vanishing moments.     

A Hybrid Compression Method for Integral Images Using Discrete Wavelet Transform and Discrete Cosine Transform

Integral imaging (II) is a promising three-dimensional (3-D) imaging technique that uses an array of diffractive or refractive optical elements to record the 3-D information on a conventional digital sensor. With II, the object information is recorded in the form of an array of subimages, each representing a slightly different perspective of the object In order to obtain high-quality 3-D images, digital sensors with a large number of pixels are required. Consequently, high-quality II involves recording and processing large amounts of data. In this paper, we present a compression method developed for the particular characteristics of the digitally recorded integral image. The compression algorithm is based on a hybrid technique implementing a four-dimensional transform combining the discrete wavelet transform and the discrete cosine transform. The proposed algorithm outperforms the baseline JPEG compression scheme applied to II and a previous compression method developed for II based on MPEG II.     

Investigation of Lifting-Based Hardware Architectures for Discrete Wavelet Transform

This paper investigates efficient hardware architectures for implementation of 1-D and 2-D discrete wavelet transforms (DWTs). The architectures are based on the lifting scheme. We propose a general structure to minimize the number of multipliers and adders for 1-D DWTs. Compared to previous conventional architectures, the architecture presented here is more efficient in terms of the required arithmetic units. Moreover, we describe a new frame scan method for a block-based 2-D DWT structure which provides a flexible trade-off between the required internal memory size and external memory access. In contrast, other 2-D DWT structures require a fixed memory size.     

An Efficient Folded Architecture for Lifting-Based Discrete Wavelet Transform

In this brief an efficient folded architecture (EFA) for lifting-based discrete wavelet transform (DWT) is presented. The proposed EFA is based on a novel form of the lifting scheme that is given in this brief. Due to this form, the conventional serial operations of the lifting data flow can be optimized into parallel ones by employing parallel and pipeline techniques. The corresponding optimized architecture (OA) has short critical path latency and is repeatable. Further, utilizing this repeatability, the EFA is derived from the OA by employing the fold technique. For the proposed EFA, hardware utilization achieves 100%, and the number of required registers is reduced. Additionally, the shift-add operation is adopted to optimize the multiplication; thus, the proposed architecture is more suitable for hardware implementation. Performance comparisons and field-programmable gate array (FPGA) implementation results indicate that the proposed EFA possesses better performances in critical path latency, hardware cost, and control complexity.     

Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Packet Transform

This brief presents a novel very large-scale integration (VLSI) architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing without any on-chip memory/first-in first out access. A folded architecture for lifting-based wavelet filters is proposed to compute the wavelet butterflies in different groups simultaneously at each decomposition level. According to the comparison results, the proposed VLSI architecture is more efficient than the previous proposed architectures in terms of memory access, hardware regularity and simplicity, and throughput. The folded architecture not only achieves a significant reduction in hardware cost but also maintains both the hardware utilization and high-throughput processing with comparison to the direct mapped tree-structured architecture     

Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems

In this paper, a novel reconfigurable discrete wavelet transform processor architecture is proposed to meet the diverse computing requirements of future generation multimedia SoC. The proposed architecture mainly consists of reconfigurable processing element array and reconfigurable address generator, featuring dynamically reconfigurable capability where the wavelet filters and wavelet decomposition structures can be reconfigured as desired at run-time. The lifting-based reconfigurable processing element array possesses better computation efficiency than convolution-based architectures, and a systematic design method is provided to generate the hardware configurations of different wavelet filters for it. The reconfigurable address generator handles flexible address generation for data I/O access in different wavelet decomposition structures. A prototyping chip has been fabricated by TSMC 0.35 μm 1P4M CMOS process. At 50 MHz, this chip can achieve at most 100 M pixels/sec transform throughput, together with energy efficiency and unique reconfigurability features, proving it to be a universal and extremely flexible computing engine for heterogeneous reconfigurable multimedia systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Liang-Gee Chen (S’84–M’86–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively. In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of VLSI Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

基于DSP的正交离散子波变换系统的设计与实现

子波变换现已成为一种重要的信号处理方法．本文提出一种以ＴＩ公司ＤＳＰ（ＴＭＳ３２０Ｃ３０）为基础的一维正交离散子波变换系统的实现方法，用该系统实现 Ｍａｌｌａｔ 正交子波快速分解与重构算法，并详细介绍了该系统的电路设计原理和相应的软件流程．测试结果表明该系统重构信号的绝对误差小于１０~( －３)。     

一种新的高速二维离散小波变换器结构

提出了一种应用于JPEG2000静态图像编码系统的二维离散小波变换(2D-DWT)单元的FPGA实现.分析了2D-DWT算法的特点,提出了一种直接进行二维小波变换的高速算法,克服了传统二维小波变换算法对存储器的频繁访问的缺点.同时,硬件结构具有较高的并行度和吞吐率;运用流水线技术,进一步提高了系统性能,每个时钟能输出4个小波系数.该结构对于N×N的图像,处理速度仅需要(N/2)2个时钟周期.设计经过FPGA验证,可用于实时图像压缩系统中.     

High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations

The main implementations of the 2-D binary-tree discrete wavelet decomposition are theoretically analyzed and compared with respect to data-cache performance on instruction-set processor-based realizations. These implementations include various image-scanning techniques, from the classical row-column approach to the block-based and line-based methods, which are proposed in the framework of multimedia-coding standards. Analytical parameterized equations for the prediction of data-cache misses under general realistic assumptions are proposed. The accuracy and the consistency of the theory are verified through simulations on test platforms and a comparison is made with the results from a real platform.     

A fast Discrete Wavelet Transform algorithm for visual processing applications

For visual processing applications, the two-dimensional (2-D) Discrete Wavelet Transform (DWT) can be used to decompose an image into four-subband images. However, when a single band is required for a specific application, the four-band decomposition demands a huge complexity and transpose time. This work presents a fast algorithm, namely 2-D Symmetric Mask-based Discrete Wavelet Transform (SMDWT), to address some critical issues of the 2-D DWT. Unlike the traditional DWT involving dependent decompositions, the SMDWT itself is subband processing independent, which can significantly reduce complexity. Moreover, DWT cannot directly obtain target subbands as mentioned, which leads to an extra wasting in transpose memory, critical path, and operation time. These problems can be fully improved with the proposed SMDWT. Nowadays, many applications employ DWT as the core transformation approach, the problems indicated above have motivated researchers to develop lower complexity schemes for DWT. The proposed SMDWT has been proved as a highly efficient and independent processing to yield target subbands, which can be applied to real-time visual applications, such as moving object detection and tracking, texture segmentation, image/video compression, and any possible DWT-based applications.     

逆向工程中对离散点云的特征识别算法探究

基于逆向设计中点云处理的表面识别问题,本文提出了一种基于小波变换的离散点云数据的特征识别算法。首先将离散点云表示成小波变换可以处理计算的形式,然后在此基础上提出了具体的二维和三维离散点云的小波分解算法,最后引入实例,对二维离散点云的小波分解算法进行验证分析。实验结果表明本文提出的算法达到了对点云数据的特征分解的目的。将离散点云数据按特征分解从而提取出不同的特征成分,可以根据后期点云预处理的不同要求,将小波变换后的数据进行进一步的处理。