带有LED故障检测功能的LED驱动器

美信公司推出带有LED故障检测功能的驱动器系列MAX6977。MAX6977串行接121LED驱动器提供8个开漏、恒流吸收、额定5．5VLED驱动器输出．采用3V～5．5V电源供电。MAX6977和LED电源能以任意顺序上电，所有恒流输出均由一个外部电阻设置，每路最大55mA。该系列产品采用25Mb，工业标准4线串口进行控制。     

通用AC输入高亮度LED驱动器件控制器MAX16801

<正> MAXIM 公司推出的 MAX16801是适合85～265V 的 AC 通用输入的高亮度的(HB)LED 驱动器控制 IC,其应用主要是一般照明和背光显示,具体包括商业和工业照明、装饰与建筑照明及 LCDTV和 LCD 监视器背光照明等。     

蓬勃发展的大功率LED驱动器

近年来,随着半导体材料及工艺技术的发展,各种LED的性能不断地提高,价位却不断地下降。在各种LED中,大功率白光LED的发展是最快的。利用大功率LED能发出各种鲜艳颜色及具有很高亮度的特点,在城市的各种建筑及景点装上了大功率LED的饰灯,使城市在夜间更亮丽;利用大功率LED有较高的发光效率及极长的工作寿命的特点,开发出各种照明灯具,并有节能减排的效果。     

液晶电视LED驱动器

LX27901是无损耗LED背光驱动器,该器件采用专有的无损耗架构,能够显著提高电源效率,同时增强背光性能并降低总体解决方案成本。其也是首款基于LCD整合式电源架构的电视提供LED驱动能力的器件。LIPS架构将电视的主电源与LED驱动器集成在一块印刷电路板上,可提供更低成本和更高效率。     

LED驱动器IC的发展趋势——来自LED驱动器供应商的访问

本文通过对各LED驱动器厂商的访问,探讨了LED驱动器市场技术发展趋势,以及照明、背光和LEDTV方面的技术特点,并有部分供应商的产品策略。     

高亮度LED驱动器

LM3450内置主动式功率因素修正器（PFC）和相位调光译码器,确保可在极宽的可编程调光范围内灯光的明暗变化稳定,不会出现闪烁情况。     

LED显示驱动器的CPLD实现

给出了一种利用电子设计自动化(EDA)软件对复杂可编程逻辑器件(CPLD)进行设计以实现8位发光二极管(LED)显示驱动器的方法.设计结果表明,用1片Lattice公司的ispLSI1032E(6 000门密度)最多可以驱动12位LED显示器.文中还就如何减少资源进行了探讨,介绍了5种方法.     

NCP1840：LED驱动器

安森美半导体推出多通道LED驱动器NCP1840,这器件能够使用用户创建的任何照明图形,独立驱动多达8颗LED。NCP1840适合于多通道LED状态指示器给用户传达状态及诊断状况,并帮助终端产品透过LED动态图形功能造出区别。     

LX27901：LED驱动器

美高森美公司推出用于液晶电视的新型突破性无损耗LED背光驱动器LX27901,该器件采用专有的无损耗架构,能够显著提高电源效率,同时增强背光性能并降低总体解决方案成本。LX27901LED驱动器基于LCD整合式电源架构的电视提供LED驱动能力的器件,LIPS架构将电视的主电源与LED驱动器集成在一块印刷电路板上。     

Pump current modulated charge pump PLL

The performance of a charge pump PLL (CP-PLL) is strongly influenced by the pump current magnitude in the pump ON interval. An examination is presented of the effect of linearly increasing pump current on the transient response of a CP-PLL. It has been observed that the process of pump current `modulation' may be used to enhance the transient behaviour of the CP-PLL     

An evaluation of MOS interface-trap charge pump as an ultralow constant-current generator

Explores the MOS interface-trap charge-pump as an ultralow constant-current generator for analog CMOS applications. Charge pumping techniques in general are more suitable than conventional continuous-time techniques for ultralow current generation because the linear controllability of current by frequency is maintained regardless of the level of current. An interface-trap pump has the same property but the minimum charge it puts out per cycle is at least two orders of magnitude smaller than that of a switched-capacitor charge pump. This helps generate the same current more accurately at a much higher frequency with a much smaller filter capacitance. The paper presents a simplified model of the terminal characteristics of the interface-trap pump and an evaluation of its performance as a stand-alone current generator. Cascoding and complementary pumping are introduced as measures of performance improvement. Temperature sensitivity, pulse feedthrough, controllability, matching, reliability, and trimming issues are addressed. Transconductor circuits built with the charge pump are presented and experimentally evaluated.     

一种降低电源峰值电流的电荷泵电路

为了降低电荷泵电路启动过程中的峰值电流,本文提出了一种具有低峰值电流的电荷泵电路。该电路中采用N-相位时钟电路,产生N个相位不交叠的时钟信号,使得电荷泵启动过程中时钟电路仅对一个电容进行充放电,从而有效减少了电源峰值电流。Hspice仿真结果表明,电荷泵电路级数为4时,所提出的电路能够将电源峰值电流减少约50%。     

Research and design of a novel current mode charge pump

To meet the demands for a number of LEDs, a novel charge pump circuit with current mode control is proposed. Regulation is achieved by operating the current mirrors and the output current of the operational transcon ductance amplifier. In the steady state, the input current from power voltage retains constant, so reducing the noise induced on the input voltage source and improving the output voltage ripple. The charge pump small-signal model is used to describe the device's dynamic behavior and stability. Analytical predictions were verified by Hspice sim ulation and testing. Load driving is up to 800 mA with a power voltage of 3.6 V, and the output voltage ripple is less than 45 mV. The output response time is less than 8 μs, and the load current jumps from 400 to 800 mA.     

电流模线性控制电荷泵的研究与设计

To meet the demands for a number of LEDs,a novel charge pump circuit with current mode control is proposed.Regulation is achieved by operating the current mirrors and the output current of the operational transconductance amplifier.In the steady state,the input current from power voltage retains constant,so reducing the noise induced on the input voltage source and improving the output voltage ripple.The charge pump small-signal model is used to describe the device’s dynamic behavior and stability.Analytical predictions were verified by Hspice simulation and testing.Load driving is up to 800 mA with a power voltage of 3.6 V,and the output voltage ripple is less than 45 mV.The output response time is less than 8μs,and the load current jumps from 400 to 800 mA.     

Single-switch electronic ballast with continuous input current charge pump power-factor correction

This paper presents a single-switch electronic ballast with continuous input current charge pump power-factor correction. The ballast circuit is composed of a series/parallel inverter, a charge pump power-factor corrector, and a dimming controller. The characteristics and design considerations of this ballast are discussed in this paper. Dimming control is achieved by varying the switching frequency. The frequency-modulation scheme is used to reduce the low-frequency output current ripple. A prototype of a 36WT8 fluorescent lamp ballast has been implemented and tested. Experimental results verify the analytical derivations.     

Reduction of current mismatching in the switches-in-source CMOS charge pump

In this paper, the charge pump (CP) based on a switches-in-source architecture is to be improved by gain-boosting amplifiers for phase-locked loops (PLLs). In our design, two differential amplifiers were employed in this CP to reduce the effect of the channel length modulation in MOS transistors. As a result, the up and down currents will be rather independent of the output voltage transformed by the capacitive low pass filter (LPF). This circuit was implemented using TSMC 0.18-μm CMOS technology and was investigated at a power supply of 1.8 V. The measured mismatch was less than 1% for the output voltage ranging from 0.4 to 1.4 V. This result is lower than that of the dynamic current-matching CP with feedback tuning on the same architecture. A comparison will be presented and discussed.     

Linearised charge pump independent of current mismatch through timing rearrangement

In conventional fractional N phase-locked loops (PLLs), charge pump nonlinearity dominates the overall loop linearity. A nonlinear charge pump increases close-in phase noise and fractional spur. Charge pump nonlinearity is mainly caused by up and down current mismatch which is in turn caused by device mismatch, and finite output impedance. A new charge pump linearisation technique is proposed by introducing an extra delay in the phase-frequency detector (PFD), so that charge nonlinearity caused by current mismatch is cancelled. The new method is independent of current mismatch. A fractional N PLL has been implemented in a 0.18 ?m CMOS technology with the proposed linearisation technique. The measured fractional spur at 300 kHz offset is -77 dBc at 3.975 GHz.     

A high current drive CMOS output stage with a tunable quiescent current limiting circuit

A CMOS output stage based on a complementary common source with an original quiescent current limiting circuit is presented. The quiescent current can be varied over a wide range by means of a control current with no need to modify the transistor aspect ratios. The output stage has been coupled to a conventional complementary input stage to form a rail-to-rail buffer. A prototype with the inclusion of auxiliary pins for biasing and current monitoring purposes has been designed using the 1-/spl mu/m double-polysilicon BCD3S process of STMicroelectronics. On a single 5-V power supply, the maximum output current is 20 mA. The amplifier, biased for a total power dissipation of 1 mW, exhibits a total harmonic distortion of -58 dB at 1 kHz with 4-V peak-to-peak on a 330-/spl Omega/ load. Correct operation of the quiescent current limiting circuit has been demonstrated for a minimum supply voltage of 2.2 V.     

Low-voltage class AB buffers with quiescent current control

This paper presents a simple class AB buffer which is suitable for low-voltage (1.5 V) applications. The proposed buffer uses an adaptive load to reduce the sensitivity of the quiescent current to the process variation. The main feature of this scheme is its simplicity. The circuit was fabricated in a 2.0 μm digital CMOS process. Experimental results demonstrate that the buffer can operate with a supply voltage below 2 V, and it has the capability to drive small resistive loads