RF CMOS reliability simulations

We present a simulation approach to assess the reliability of an RF CMOS circuit under user conditions, based on existing DC degradation models for gate-oxide breakdown and hot-carrier degradation. The simulator allows for lifetime prediction of circuits that can withstand multiple breakdown events. Simulation results show that three power amplifiers with comparable initial circuit performance show an astronomic difference in reliability. The tool thus proves to be an asset in the analog design process.     

基于40nm CMOS工艺电路的NBTI退化表征方法

负偏压温度不稳定性(NBTI)退化是制约纳米级集成电路性能及寿命的主导因素之一,基于40 nm CMOS工艺对NBTI模型、模型提参及可靠性仿真展开研究。首先对不同应力条件下PMOS晶体管NBTI退化特性进行测试、建模及模型参数提取,然后建立了基于NBTI效应的VerilogA等效受控电压源,并嵌入Spectre^TM仿真库中,并将此受控电压源引入反相器及环形振荡器模块电路中进行可靠性仿真分析,可有效反映NBTI退化对电路性能的影响。提出了一套完整可行的电路NBTI可靠性预测方法,包括NBTI模型、模型参数提取、VerilogA可靠性模型描述以及电路级可靠性仿真分析,可为纳米级高性能、高可靠性集成电路设计提供有效参考。     

Improved reliability of bistable circuits by selective hot-carrier stress reduction

The performance and reliability of submicron CMOS circuits have been affected by hot-carrier stress induced degradation. Three common forms of CMOS latch circuits designed using a 0.7-micron commercial process have been considered in a comparative study of the stress levels experienced by individual devices in the circuit. Average stress levels on all the devices over a typical simulation cycle was used to assess the life-time and the reliability of the circuits. We describe a technique that was used to identify the devices having higher than normal stress which may consequently degrade at a faster rate than other devices leading to an early failure of the circuit. We have developed design techniques that can be used to reduce the stress levels in identified devices. The improvements in life-time and reliability have been assessed and analysed. The best circuit configuration to reduce hot-carrier stress induced degradation has been identified.     

基于试验设计技术的IC可靠性优化设计

现代IC设计对设计者提出了更多要求,不仅要求电路满足特定功能,而且还需要满足高质量和可靠性的要求.集成电路可靠性设计的目标是使性能对不可控因素不敏感,仅依靠EDA仿真很难完成这类设计.本文探讨了利用响应曲面(RSM)统计试验设计(DOE)与电路仿真相结合对集成电路进行可靠性优化设计的方法.并将该方法应用于电压带隙基准电路可靠性优化设计.优化确定的参数组合在满足电路指标同时,对温度的变化更加不敏感,提高了电路的可靠性要求.     

Integrated-circuit reliability simulation with emphasis on hot-carrier effects

Reliability assurance and enhancement of analog VLSI circuits are of fundamental importance in the design of high quality signal processing and computing systems. An analog integrated circuit may fial due to degradation of some critical transistors. In this paper, strategies for use in a hierarchical reliability simulation environment covering various levels of VLSI circuit design are presented. Hot-carrier effects are used to demonstrate the prediction of degradation in circuit performance. This degradation information is propagated through the design hierarchy, with the data at each stage conforming with the complexity of representation at that stage. Circuit topology changes may be made at different levels to reduce the intensive electrical stress applied to weak components. At the top level the chip degradation information is essential for the design of reliable VLSI systems. The method used to include the first-order ac degradation effects into the circuit reliability simulator is described. Experimental results on inverters, precharging circuitry for sense amplifiers, and operational amplifiers designed in submicron technologies are presented.This research was partially supported by National Science Foundation under grant MIP-8710825 and by industrial grants from Samsung Electronics Co. and TRW Inc.     

An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells

Aggressive technology scaling causes unavoidable reliability issues in modern high-performance integrated circuits. The major reliability factors in nanoscale VLSI design is the negative bias temperature instability (NBTI) degradation and soft-errors in the space and terrestrial environment. In this paper, an on-chip analog adaptive body bias (OA-ABB) circuit to compensate the degradation due to NBTI aging is presented. The OA-ABB is used to compensate the parameter variations and improves the SRAM circuit yield regarding read current, hold SNM, read SNM, write margin and word line write margin (WLWM). The OA-ABB consists of standby leakage current sensor circuit, decision circuit and body bias control circuit. Circuit level simulation for SRAM cell is performed for pre- and post-stress of 10 years NBTI aging. The proposed OA-ABB reduces the effect of NBTI on the stability of SRAM cell. The simulation results show the hold SNM, read SNM and WLWM decreases by 10.55%, 8.55%, and 3.25% respectively in the absence of OA-ABB whereas hold SNM, read SNM and WLWM decreases by only 0.61%, 1.48%, and 0.72% respectively by using OA-ABB to compensate the degradation. The figure of merit of 6T SRAM cell also improved by 17.24% with the use of OA-ABB.     

Aging signature properties and an efficient signature determination tool for online monitoring

Increased reliability problems in deep sub-micron CMOS technologies have led to a dramatic decrease of lifetime of analog integrated circuits. To palliate this problem, several reliability-aware design approaches have been developed. Reconfigurable circuit design is one of those approaches, which is based on reconfiguring the circuit considering degradation in circuit performances. Sense & React (S & R) approach is the well-known reconfigurable design approach, where degradation in circuit performances are sensed and a pre-established recovery operation is applied to heal the circuit. In practice, indirect measurements are preferred during sense operation, in which electrical quantities are measured in order to determine time to recovery. Determination of the time to recover is the most critical part of a S & R system. One or more circuit variables are selected out of all measurable circuit quantities. The selected signature should have some attributes to be used as the aging signature to reduce the measurement cost. However, efficient aging signature properties have not been defined in the literature yet. Moreover, the designer determines the aging signature manually by performing an iterative search and evaluation on aging simulation results, and there is no tool to ease this time consuming process. This paper clearly describes the aging signature properties and proposes an automatic signature selection tool that determines the most efficient signature for sense operation.     

Reliability enhancement of digital combinational circuits based on evolutionary approach

Reliability has become an integral part of the system design process, especially for those systems with life-critical applications such as aircrafts and spacecraft flight control. The recent rapid growth in demand for highly reliable digital circuits has focused attention on tools and techniques we might use to enhance the reliability of the circuit. In this paper, we present an algorithm to improve the reliability of digital combinational circuits based on evolutionary approach. This method generates a global VHDL file for the selected initial set of components based on inserting multiplexers at the gate inputs of the circuit which helps to perform the simulations in only one session. This simulation framework is combined with single-pass reliability analysis approach to implement the evolutionary algorithm. The search space of the genetic algorithm is limited by the idea of slicing the initial set of components and also circuit partitioning could be used to further overcome the scalability limitations. The framework is applied to a subset of combinational benchmark circuits and our experiments demonstrate that higher reliabilities can be achieved while other factors such as power, speed and area overhead will remain admissible.     

NBTI degradation and its impact for analog circuit reliability

A methodology to quantify the degradation at circuit level due to negative bias temperature instability (NBTI) has been proposed in this work. Using this approach, a variety of analog/mixed-signal circuits are simulated, and their degradation is analyzed. It has been shown that the degradation in circuit performance is mainly dependent on the circuit configuration and its application rather than the absolute value of degradation at the device level. In circuits such as digital-to-analog converters, NBTI can pose a serious reliability concern, as even a small variation in bias currents can cause significant gain errors.     

Reliability of majority voting based VLSI fault-tolerant circuits

The effect of compensating module faults on the reliability of majority voting based VLSI fault-tolerant circuits is investigated using a fault injection simulation method. This simulation method facilitates consideration of multiple faults in the replicated circuit modules as well as the majority voting circuits to account for the fact that, in VLSI implementations, the majority voting circuits are constructed from components of the same reliability as those used to construct the circuit modules. From the fault injection simulation, a survivability distribution is obtained which, when combined with an area overhead expression, leads to a more accurate reliability model for majority voting based VLSI fault-tolerant circuits. The new model is extended to facilitate the calculation of reliability of fault-tolerant circuits which have sustained faults but continue to operate properly. Analysis of the reliability model indicates that, for some circuits, the reliability obtained with majority voting techniques is significantly greater than predicted by any previous model     

Efficient reliability evaluation methodologies for combinational circuits

Reliability evaluation methodologies have become important in circuit design. In this paper, we focus on the probabilistic transfer matrix (PTM), which has proven to be a gate-level approach for accurately assess the reliability of a combinational circuit with penalty in simulation runtime and memory usage. In order to improve its efficiency, several methodologies based on traditional PTM are proposed. A general tool is developed to calculate the reliability of a circuit with efficient computation methods based on an optimized PTM (denoted as ECPTM), which achieves runtime and memory usage improvement. Experiments demonstrate how the proposed simulation framework, combined with traditional PTM method, can provide significant reduction in computation runtime and memory usage with different benchmark circuits.     

Electrical aging behavioral modeling for reliability analyses of ionizing dose effects on an n-MOS simple current mirror

Nowadays, a deterministic approach based on physics of failure is necessary to estimate the lifetime of integrated circuits. Therefore, the reliability analyses via electrical/aging simulations are performed during the design phase. Our previous works consisted in generating an aging behavioral model of a circuit in order to assess its degradation level and to predict its lifetime according to its mission profile. This paper presents obtained experimental results using our developed methodology to evaluate the influence of total ionizing dose effects on an n-MOS simple current mirror taking into account technological dispersions.     

基于FPGA的电子表决器电路的设计与实现

为解决传统的电子表决器电路不易扩展的问题,采用VHDL语言完成了8输入和10输入的电子表决器电路的程序设计。采用FPGA芯片通过编程实现显示电路的设计,通过电路仿真分析验证了电路设计的可行性。并经由EDA编程设计使电路结构简单、便于扩展、可靠性高、可移植性强、易于实现。     

Design considerations for CMOS digital circuits with improvedhot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability     

Low-temperature operation of Ge picosecond logic circuits

Low temperature operation of emitter-coupled logic circuits offers potential advantages in reliability, noise immunity, power dissipation, and speed. Experimental picosecond germanium integrated circuits exhibit significant improvements in delay with moderate cooling, in contrast to observed degradation in the performance of comparable silicon circuits. The results of a study of the design factors and performance of germanium circuits at low temperatures are described, with comparisons to silicon. The effect of temperature on circuit propagation delay is emphasized. Brief discussions are included relating observed circuit and transistor temperature dependences to those of more fundamental parameters and processes.     

Minimizing detection-to-boosting latency toward low-power error-resilient circuits

Dynamic voltage scaling (DVS) has become one of the most effective approaches to achieve ultra-low-power SoC. To eliminate timing errors arising from DVS, several error-resilient circuit design techniques were proposed to detect and/or correct timing violations. The most recently proposed time-borrowing-and-local-boosting (TBLB) technique has the advantage of lower power consumption and less performance degradation due to the needlessness of pipeline stalls. On the other hand, to make the best use of the TBLB technique, the latency from error detection to voltage boosting for TBLB latches must be carefully considered, especially during physical design. To address this issue, this paper first introduces the behavior of TBLB circuits, and then presents two major design styles of TBLB latches, including TBLB macros and multi-bit TBLB latches, for reducing detection-to-boosting latency. The corresponding physical synthesis methodologies for both design styles are further proposed. Experimental results based on the IWLS benchmarks show that the proposed physical synthesis approach for resilient circuits with multi-bit TBLB latches is very effective in reducing the delay of both combinational and error-detection circuits, which indicates better circuit reliability. To our best knowledge, this is the first work in the literature which introduces the physical synthesis methodologies for TBLB resilient circuits.     

SCRAP: Sequential circuits reliability analysis program

The recent rapid growth in demand for highly reliable digital circuits has focused attention on tools and techniques we might use to accurately estimate the reliability of a proposed circuit on the basis of failure rate of the utilized technology. Reliability analysis has become an integral part of the system design process, especially for those systems with life-critical applications such as aircrafts and spacecraft flight control. In this paper, we present an algorithm to evaluate the reliability of sequential circuits. This approach called ‘multiple-pass’ combines gate failure probability with the propagated errors to calculate the reliability of every nodes of the circuit in an iterative manner. The proposed approach is used to implement and develop the SCRAP program. It computes the reliability of the sequential circuit based on its standard cell library which can be extended to have larger gates such as D flip-flops. The framework is applied to a subset of sequential benchmark circuits and the observed results demonstrate the accuracy and speed of the proposed technique.     

现代电子设备的可靠性设计技术

可靠性设计是现代电子设备可靠性保证体系的关键环节。阐述了电子设备可靠性设计的基本原则与实施途径，包括元器件的可靠性选用、电子线路的可靠性设计以及印制电路板的可靠性设计等。     

Improved circuit technique to reduce hfe degradation inbipolar output drivers

h_fe degradation in bipolar transistors caused by reverse V_be stress decreases the reliability of BiCMOS circuits. In this paper, we present an improved circuit technique to limit reverse V_be, and thus significantly increase BiCMOS reliability. The technique also reduces the base-emitter breakdown voltage constraint on BiCMOS technology design     

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。