Utilization of an electron beam resist process to examine theeffects of asymmetric gate recess on the device characteristics ofAlGaAs/InGaAs PHEMTs

The DC and microwave characteristics of two sets of AlGaAs/InGaAs PHEMTs having a gate length of 0.2 μm are compared. The first set is composed of devices fabricated using a trilayer electron beam resist process for T-gate recess and metallization. The second set is composed of devices fabricated using a new four-layer electron beam resist process which enables the asymmetric placement of a T-gate in a wide recess trench. Devices fabricated using the four-layer resist process showed improved breakdown voltage, lower gate-drain feedback capacitance, lower output conductance, and higher f_max with only slight reduction of drain current and transconductance. For example, the off-state drain-source breakdown voltage increased from 5.2 to 12.5 V, and the f_max, increased from 133 to 158 GHz as the drain side cap recess, L_ud, was increased from 0 to 0.55 μm     

GaAs power FET's having the gate recess narrower than the gate

GaAs power FET's have been fabricated with the gate recess narrower than the gate. The fabrication process for this new channel structure is described and microwave performance is presented. The best device had greater than 1 W output power per millimeter gate width at 10 GHz.     

Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

Damage-free reactive ion etching of GaAs FET gate recess

A GaAs reactive ion etching process is described which has good uniformity and causes no significant electrical damage to the underlying substrate. The process is shown to be suitable for forming the gate recess of a GaAs MESFET. FETs fabricated using the process exhibit DC and RF performance similar to equivalent wet etched devices.<>     

n/sup +/-InAs-InAlAs recess gate technology for InAs-channel millimeter-wave HFETs

We report a submicrometer, self-aligned recess gate technology for millimeter-wave InAs-channel heterostructure field effect transistors. The recess gate structure is obtained in an n/sup +/-InAs-InAlAs double cap layer structure with a citric-acid-based etchant. From molecular-beam epitaxy-grown material functional devices with 1000-, 500-, and 200-nm gate length were fabricated. From all three device geometries we obtain drive currents of at least 500 mA/mm, gate leakage currents below 2 mA/mm, and RF-transconductance of 1 S/mm. For the 200-nm gate length device f/sub /spl tau// and f/sub max/ are 162 and 137 GHz, respectively. For the 500-nm gate length device f/sub /spl tau// and f/sub max/ are 89 and 140 GHz, respectively. We observe scaling limitations at 200-nm gate length, in particular a negative threshold voltage shift from -550 to -810 mV, increased kink-effect, and a high gate-to-drain capacitance of 0.5 pF/mm. The present limitations to device scaling are discussed.     

Low-noise properties of dry gate recess etched InP HEMTs

Lattice-matched InAlAs-InGaAs HEMTs with dry etched and wet etched gate recesses have been fabricated and both high-frequency and noise measurements have been carried out. The highly selective dry etching process ensures uniform device parameters. The small signal and noise performance shows only minor differences between the two transistor types. There is no evidence of detrimental effects caused by dry etching that reduce the electrical and noise performance of the device at high frequencies. These results show that dry etched InP HEMT's have suitable characteristics for the fabrication of MM-wave integrated circuits     

30-nm two-step recess gate InP-Based InAlAs/InGaAs HEMTs

Two-step recess gate technology has been developed for sub-100-nm gate InP-based InAlAs/InGaAs high-electron mobility transistors (HEMTs). This gate structure is found to be advantageous for the preciseness of the metallurgical gate length as well as a comparable stability to the conventional gate structure with an InP etch stop layer. The two-step recess gate is optimized focusing on the lateral width of the gate recess. Due to the stability of the gate recess with an InP surface, a laterally wide gate recess gives the maximum cutoff frequency, lower gate leakage current, smaller output conductance and higher maximum frequency of oscillation. Finally, the uniformity of the device characteristics evaluated for sub-100-nm HEMTs with the optimized recess width. The result reveals the significant role of the short channel effects on the device uniformity.     

Study of enhancement-mode GaN pFET with H plasma treated gate recess

This letter showcases the successful fabrication of an enhancement-mode (E-mode) buried p-channel GaN field-effect-transistor on a standard p-GaN/AlGaN/GaN-on-Si power HEMT substrate. The transistor exhibits a threshold voltage (V_TH) of −3.8 V, a maximum ON-state current (I_ON) of 1.12 mA/mm, and an impressive I_ON/I_OFF ratio of 10⁷. To achieve these remarkable results, an H plasma treatment was strategically applied to the gated p-GaN region, where a relatively thick GaN layer (i.e., 70 nm) was kept intact without aggressive gate recess. Through this treatment, the top portion of the GaN layer was converted to be hole-free, leaving only the bottom portion p-type and spatially separated from the etched GaN surface and gate-oxide/GaN interface. This approach allows for E-mode operation while retaining high-quality p-channel characteristics.     

Two-layer resist structure for electron-beam fabrication of a submicrometer gate length GaAs device

A two-layer resist structure using EBR-9 and PMMA for fabricating a fine metal line with a mushroom-like cross-sectional profile is reported. The structure provides T-shaped resist cavities with undercut profiles using electron-beam exposure. With the optimum developing condition, the bottom opening is as small as 0.1 µm, and the top opening is wide enough not to require an additional exposure in order to obtain a mushroom-like metal lift-off pattern. A Monte Carlo calculation is carried out in order to analyze the profile of the two-layer resist structure, and it is shown that an undercut T-shaped resist profile with a 0.1-µm bottom opening can be obtained using a high-sensitivity resist on a low-sensitivity resist structure. A 0.15-µn mushroom-like lift-off metal profile has been fabricated on a 0.1-µm recessed GaAs substrate by the use of this resist structure.     

Modeling of oxide breakdown from gate charging during resist ashing

Plasma damage was observed after exposing an antenna capacitor structure to an O₂ plasma in a single wafer resist asher. The observed early breakdown is well modeled by surface charging caused by plasma nonuniformity. Here, the plasma nonuniformity was induced by gas flow and electrode configuration. The present results agree well with our previous results where magnetic field leads to a nonuniform plasma. In this model, nonuniformity leads to a local imbalance of ion and electron currents which charge up the gate surface and degrade the gate oxide. Using SPICE, a circuit model for the test structure and plasma measurements, the Fowler-Nordheim current through the thin oxide regions at different points on the wafer was calculated and found to agree well with the observed damage. The important implication of this work on oxide reliability is that the modeling gives a clear picture to this breakdown mechanism. The charging model can also be applied to any ashing process in any nonuniform plasma. Moreover, this model provides a physical basis for design rules of device structures for the fabrication of reliable gate oxides in submicron MOS technology     

A novel self-aligned gate process for half-micrometer gate GaAs ICsusing ECR-CVD

A substitutional self-aligned gate MESFET process for the half-micrometer gate GaAs IC that employs techniques of sidewall formation and precise pattern reversal using ECR (electron cyclotron resonance) CVD (chemical vapor deposition) is discussed. A FET with 0.45-μm gate length showed high performance characteristics, such as a maximum transconductance of 440 mS/mm and a cutoff frequency of 39 GHz. This process has two advantages over conventional substitutional and refractory gate processes. First, it can incorporate an LDD (lightly doped drain) structure. Second, since the photoresist dummy gates are precisely reversed without using reactive ion etching (RIE) at all, the gate length is dependent only on lithography. The process was demonstrated by the preliminary fabrication of a 16 b×16 b multiplier with 50% yield. The process, with high-performance device characteristics, should fine broad applications in both half-micrometer gate level LSIs and analog ICs     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Independent double-gate FinFETs with asymmetric gate stacks

Flexibly controllable threshold voltage (V_th) asymmetric gate oxide thickness (T_ox) independent double-gate (DG) FinFETs (4T-FinFETs) have been demonstrated. Thin drive-gate oxide (HfO₂ or SiON or SiO₂) and slightly thick V_th-control-gate oxide (thick SiO₂+drive-gate oxide) have been successfully incorporated into the 4T-FinFETs by utilizing the ion-bombardment-enhanced etching of SiO₂. It was experimentally confirmed that, all the asymmetric T_ox 4T-FinFETs give the significantly improved subthreshold slope and thus gain higher on-current as compared to the symmetric one. Simulation results showed that the asymmetric T_ox 4T-FinFETs are advantageous even in 20-nm-gate-length region.     

High-pressure oxidation for thin gate insulator process

High-pressure oxidation of silicon was performed at a pressure of 8.9 kg/cm²at a temperature range of 650 to 950°C. The oxidation temperature dependence of the film density, refractive index, chemical etching rate, and residual stress was measured. The film density of the oxide film was found to increase with decreasing oxidation temperature. The refractive index of the film also increased with decreasing oxidation temperature. The residual stress was found to be dependent on the oxidation temperature. The dielectric breakdown strength of the oxide film was measured by the voltage ramping method. The defect density of the oxide film calculated from the distribution of dielectric breakdown strength slightly decreased with decreasing oxidation temperature. The surface-state density of the oxide film was about 1.1 × 10¹¹cm^-2throughout the oxidation temperature range. The oxide grown on a doped polysilicon layer at a temperature of 750°C was five times as thick as the oxide simultaneously grown on the silicon substrate. The high-pressure and low-temperature oxidation was applied to the fabrication process of a device with a double polysilicon layer structure.     

DPN MOS绝缘栅氮处理技术

分析了90nm及其以上技术、栅氧化及其氮处理工艺的局限性,强调了等离子体氮处理技术在90nm及其以下技术中的必要性.介绍了应用材料公司DPN MOS绝缘栅氮处理技术,并出示了部分试验数据.     

Novel interface nitridation process for thin gate oxides

A thin (100-200-Å) gate dielectric film which exhibits improved properties as compared to control pure thermal oxides is discussed. The film is obtained by thermal nitridation of the silicon wafers in pure ammonia, followed by high temperature oxide (HTO) deposition, and an anneal in oxygen ambient (reoxidation). It was found that these dielectrics exhibit excellent electrical characteristics under Fowler-Nordheim tunneling stress, such as a relatively large charge-to-breakdown considerable reduction in charge trapping, reduction of interface state generation, and a significantly improved resistance to transconductance degradation. The dielectric layer is of potential use for the fabrication of reliable ultrathin gate oxide films for standard CMOS technology and particularly for nonvolatile programmable memories     

A new tungsten gate process for VLSI applications

In spite of the growing demand for MOS gates and interconnections of higher conductivity, the refractory metal gate process has not received as much attention as those using silicides because it is incompatible with the Si-gate process. The metal gate cannot withstand oxidizing annealing ambients, and source-drain formation by ion implantation is difficult because of the channeling of doping ions through the gate metal during ion implantation. In a new process developed for use in MOS VLSI fabrication, tungsten (W) is used as a gate metal because degradation of SiO2by annealing the metal/SiO2/Si structure at around 1000°C can be minimized if the metal is W. Metal oxidation is prevented by using a H2/H2O ambient for this annealing, which also allows Si to be oxidized in the same ambient. The channeling mentioned above is stopped by forming a thin layer of PSG or WOxon the W. This gate process is believed to be a step forward toward the desired compatibility.     

A surface potential based drain current model for asymmetric double gate MOSFETs

In this paper, we present a generic surface potential based current voltage (I-V) model for doped or undoped asymmetric double gate (DG) MOSFET. The model is derived from the 1-D Poisson’s equation with all the charge terms included and the channel potential is solved for the asymmetric operation of DG MOSFET based on the Newton-Raphson iterative method. A noncharge sheet based drain current model based on the Pao-Sah’s double integral method is formulated in terms of front and back gate surface potentials at the source and drain end. The model is able to clearly show the dependence of the front and back surface potential and the drain current on the terminal voltages, gate oxide thicknesses, channel doping concentrations and the Silicon body thickness and a good agreement is observed with the 2-D numerical simulation results.     

The role of resist for ultrathin gate oxide degradation during O2 plasma ashing

During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect. Recently, we found instead that resist does not simply act as a protection layer. This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study. Here we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer. The experimental results show a good correlation with our explanation. To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period