基于0.18μm CMOS工艺的0.1-2GHz宽带功率放大器芯片

本文介绍了一种基于0.18μm CMOS工艺的0.1–2 GHz宽带射频功率放大器(PA)。该PA采用了双级、晶体管堆叠放大器结构结合电阻匹配和负反馈技术,可以在较小的芯片面积内实现良好的功率增益、增益平坦度和宽带匹配特性。实测结果表明,在5 V供电时,该PA可以在0.1–2 GHz频段内实现18.1±0.6 dB的增益、优于10.5 dB的输入匹配、优于12.6 dB的输出匹配、12%的功率附加效率和优于20 dBm的输出功率。该PA芯片面积仅占用0.52 mm~2,是目前作者所知覆盖该频段并同时实现上述指标的最小面积的CMOS PA芯片。     

Ka 波段连续波 9W GaN 功率放大器

本文研制了一款采用 0. 15 μm 碳化硅基氮化镓功率 MMIC 工艺的 Ka 波段连续波功率放大器芯片。功率放大器采用了 3 级共源级联结构。 输出级采用了 16 个晶体管进行功率合成,有效地分散了热分布,输出匹配网络采用低损耗拓扑架构,保证了输出功率与附加效率。 级间匹配采用了最大增益匹配,同时兼顾了小信号增益平坦度。 在28 GHz~30 GHz内,小信号增益为 25 dB,28 V 偏置电压下连续波输出功率大于 39 dBm,功率增益为 17 dB,附加效率大于 25%,热阻为1. 41 ℃ /W。 输出功率为 35 dBm 时,IMD3 小于-25 dBc,芯片面积为 3. 0 mm×3. 1 mm。     

75 GHz 13.92 dBm InP DHBT 共射共基功率放大器

报道了基于InP基双屏质结双板晶体管(DHBT)工艺的四指共射共基75 GHz微波单片集成(MMIC)功率放大器,器件的最高振荡频率fmax为150 GHz.放大器的输出极发射极面积为15μm×4μm.功率放大器在75 GHz时功率增益为12.3 dB,饱和输出功率为13.92 dBm.放大器在72.5 GHz处输入为2 dBm时达到最大输出功率14.53 dBm.整个芯片传输连接采用共面波导结构,芯片面积为1.06 mm×0.75 mm.     

X波段60W高效率GaN HEMT功率MMIC

研制了一款采用0.25μm GaN功率MMIC工艺研制的X波段高效率功率放大器芯片。芯片采用三级放大拓扑结构设计。末级匹配电路采用电抗匹配方式兼顾输出功率和效率,同时优化驱动级和末级管芯栅宽比以及级间匹配电路,降低驱动级管芯电流。通过这两种技术途径有效提高芯片的功率附加效率。输入级和级间匹配电路采用有耗匹配方式,扩展工作带宽以及提高稳定性。芯片在8~12GHz频带范围内漏压28V,脉宽100μS,占空比10%工作条件下输出功率达到47.5~48.7dBm,功率增益大于20dB,功率附加效率40%~45%。芯片面积3.5mm×3.8mm,单位面积功率密度为5.57 W/mm2,连续波条件下热阻为1.7K/W。     

19WC-波段MMIC多芯片合成功率放大器

报告了一个两级 C-波段功率单片电路的设计、制作和性能 ,该单片电路包括完全的输入端和级间匹配 ,输出端的匹配在芯片外实现 ,该放大器在 5.2～ 5.8GHz带内连续波工作 ,输出功率大于 36.6d Bm,功率增益大于 18.6d B,功率附加效率 34 % ,4芯片合成的功率放大器在 4 .7～ 5.3GHz带内 ,输出功率大于 4 2 .8d Bm( 19.0 W) ,功率增益大于 18.8d B,典型的功率附加效率为 34 %。     

2.4GHz全集成CMOS Doherty功率放大器

采用0.18μm CMOS工艺设计并制作了一个2.4 GHz全集成CMOS Doherty功率放大器.着重考虑了片上螺旋电感的回流路径对电感模型的影响,并在设计中使用了一种新颖的螺旋电感版图结构来避免回流路径的影响.实测结果表明该功率放大器增益达到16dB,1dB压缩点为20.5dBm,峰值输出功率和对应功率附加效率分别为21.2dBm和20.4％,整个芯片面积为2.8mm×1.7mm.     

基于中和电容的60 GHz CMOS功率放大器设计

功率放大器（Power Amplifier, PA）是射频前端重要的模块,本文基于SMIC 55 nm RF CMOS 工艺,设计了一款60 GHz 两级差分功率放大器。针对毫米波频段下,硅基CMOS晶体管栅漏电容（Cgd）严重影响放大器的增益和稳定性的问题,采用交叉耦合电容中和技术抵消Cgd影响。通过优化级间匹配网络和有源器件参数,提高了功率放大器的输出功率,增益和效率。后仿结果显示,在1.2V的供电电压下,工作在60 GHz的功率放大器饱和输出功率为11.3 dBm,功率增益为16.2 dB,功率附加效率为17.0%,功耗为62 mW。芯片面积380×570 um2 。     

一种65 nm CMOS 60 GHz高增益功率放大器

设计了一种基于65 nm CMOS工艺的60 GHz功率放大器。采用共源共栅结构与电容中和共源级结构相结合的方式来提高功率放大器的增益,并采用两路差分结构来提高输出功率。采用片上变压器作为输入/输出匹配及级间匹配,以减小芯片的面积,从而降低成本。采用Cadence、ADS和Momentum等软件进行联合仿真。后仿真结果表明,在工作频段为60 GHz时,最大小信号增益为26 dB,最大功率附加效率为18.6%,饱和输出功率为15.2 dBm。该功率放大器具有高增益、高效率、低成本等优点。     

一种高线性宽带功率合成的射频功率放大器

针对5G通信微基站,提出一种基于GaAs异质结双极晶体管（HBT）工艺,芯片面积为1.3 mm×1.4 mm的高线性宽带宽的射频功率放大器。该放大器采用了异相功率合成方式和J类输出匹配的方法,在两路功率放大器的输入输出端引入了90°相移以及J类模式确定最佳负载阻抗,以此实现高线性宽带宽的特性。在5 V电源和2.85 V偏置电压下,室温条件下测试结果表明,该功率放大器在2～3 GHz频带内,小信号增益为36±0.5 dB。然而在2.4～2.8 GHz频带内,该功率合成结构的功率放大器拥有饱和输出功率大于36 dBm,功率附加效率大于38%。在5G-NR,带宽100 MHz和4G-LTE、带宽20 MHz的调制信号下,在2.4～2.8 GHz工作频带测试,放大器的输出功率为22 dBm,邻近信道功率比（ACPR）约为-43 dBc。     

工作在1.8-3 GHz内的高效率GaAs pHEMT功率单片

本文报道了一款基于南京电子器件研究所GaAs pHEMT单片集成电路工艺的S波段宽带高效率功率放大器。为了提高芯片效率,该放大器采用驱动比为1:8的两级级联方式,并采用低通/高通滤波器相结合的拓扑结构设计每级的匹配电路。这种匹配电路在有效降低芯片面积的同时,在较宽的频带范围内实现对应于高效率的阻抗匹配。在5V漏压AB类偏置条件下,该功率放大器在1.8到3GHz频率范围内连续波输出饱和功率为33~34 dBm,相应的附加效率达到35%~45%,以及非常平坦的功率增益25~26 dB。芯片面积紧凑,尺寸仅为2.7mm×2.75mm。     

A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

In this letter, a fully integrated 20-dBm RF power amplifier (PA) is presented using 0.25-mum-gate silicon-on-sapphire metal-oxide-semiconductor field-effect transistors (MOSFETs). To overcome the low breakdown voltage limit of MOSFETs, a stacked FET structure is employed, where transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the optimum load impedance for a 20-dBm PA increases to 50Omega, which is nine times higher than that of parallel FET topology for the same output power. Measurement of a single-stage linear PA shows small-signal gain of 17.1 dB and saturated output power of 21.0dBm with power added efficiency (PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access modulated signal, the PA shows an average output power of 16.3 dBm and PAE of 18.7% with adjacent channel power ratio below -42dBc     

A 18 GHz Broadband Stacked FET Power Amplifier Using 130 nm Metamorphic HEMTs

A broadband power amplifier (PA) with a 3 dB power bandwidth of 72% is presented using metamorphic high electron mobility transistors (mHEMTs). A stacked FET structure, where transistors are series connected to combine voltage swings, is employed to overcome relatively low breakdown voltages of mHEMTs. Series-connected PA's show much higher load impedance compared to the parallel combined transistors, which allows output matching to be realized in the low quality (Q)-factor region, providing the broadband performance. The fabricated PA using quadruple-stacked 130 nm mHEMTs has a gain of 21.2 dB and saturated output power of 26.4 dBm with power added efficiency (PAE) of 33% at the design frequency of 18 GHz. The 3 dB output power bandwidth is from 10 to 23 GHz.      

Power-amplifier modules covering 70-113 GHz using MMICs

A set of W-band power amplifier (PA) modules using monolithic microwave integrated circuits (MMICs) have been developed for the local oscillators of the far-infrared and sub-millimeter telescope (FIRST). The MMIC PA chips include three driver and three PAs, designed using microstrip lines, and another two smaller driver amplifiers using coplanar waveguides, covering the entire W-band. The highest frequency PA, which covers 100-113 GHz, has a peak power of greater than 250 mW (25 dBm) at 105 GHz, which is the best output power performance for a monolithic amplifier above 100 GHz to date. These monolithic PA chips are fabricated using 0.1-μm AlGaAs/InGaAs/GaAs pseudomorphic T-gate power high electron-mobility transistors on a 2-mil GaAs substrate. The module assembly and testing, together with the system applications, is also addressed in this paper     

高性能1mm AlGaN/GaN功率HEMTs研制

报道了基于蓝宝石衬底的高性能1mm AlGaN/GaN HEMTs功率器件.为了提高微波功率器件性能，采用新的欧姆接触和新型空气桥方案．测试表明，器件电流密度为0.784A/mm，跨导197mS/mm，击穿电压大于40V，截止态漏电较小，1mm栅宽器件的单位截止频率达到20GHz，最大振荡频率为28GHz，功率增益为11dB，功率密度为1.2W/mm,PAE为32%,两端口阻抗特性显示了在微波应用中的良好潜力．     

一种用于5G通信的高稳定双模功率放大器

采用国产40 nm CMOS工艺,设计了一种用于5G通信的28 GHz双模功率放大器。功率级采用大尺寸晶体管,获得了高饱和输出功率。采用无中心抽头变压器,消除了大尺寸晶体管带来的共模振荡问题。在共源共栅结构的共栅管栅端加入大电阻,提高了共源共栅结构的高频稳定性。采用共栅短接技术,解决了大电阻引起的差模增益恶化问题。在级间匹配网络中采用变容管调节,实现了双模式工作,分别获得了高功率增益和高带宽。电路后仿真结果表明,在高增益模式下,该双模功率放大器获得了20.8 dBm的饱和输出功率、24.5%的功率附加效率和28.1 dB的功率增益。在高带宽模式下,获得了20.6 dBm的饱和输出功率、22.6%的功率附加效率和12.2 GHz的3 dB带宽。     

简洁构型与馈电的宽带双极化金属锥阵列天线北大核心CSCD

本文提出了一种宽带双极化金属锥阵列天线。该阵列天线以传统的旋转体天线结构为主体,通过在锥体底部开设四道正交的直通槽,以便在锥状单元内部形成可与地板间构成匹配谐振腔的开放式空腔结构。在阵列中,任意两个相邻的锥状单元之间可形成类似于Vivaldi天线的辐射缝隙结构。馈电采用同轴馈电方式,探针无弯折结构,金属锥体无弯折过孔。每个金属锥状单元独立,可极大简化加工、装配和维护过程。该天线具有两个正交极化,分别由左右和前后相邻单元构成。仿真结果表明,在频率范围为2～8GHz内,阵列大部分有源VSWR小于2,小部分端口有源VSWR小于2.5 (相对带宽为120%)。     

大信号设计GaAs MESFET功率合成

利用ＧａＡｓＭＥＳＦＥＴ功率特性的线性化模型，求出ＧａＡｓＭＥＳＦＥＴ近似最佳功率负载阻抗，为利用谐波平衡法计算提供初值。然后，使用自行研制的谐波平衡分析软件包，进行ＧａＡｓＭＥＳＦＥＴ大信号模型参数的提取和非线性电路模拟计算。将两只总栅宽为９．６ｍｍ的ＧａＡｓＭＥＳＦＥＴ管芯，利用内匹配功率合成技术，在Ｃ波段（５．５～５．８ＧＨＺ）制成１ｄＢ压缩功率大于８Ｗ，典型功率增益９ｄＢ的ＧａＡｓＭＥＳＦＥＴ内匹配功率管。     

A Compact 6.5-W PHEMT MMIC Power Amplifier for Ku-Band Applications

A compact 6.5-W AlGaAs/InGaAs/GaAs PHEMT monolithic microwave integrated circuit (MMIC) power amplifier (PA) for Ku-band applications is proposed. This two-stage amplifier with chip size of 8.554mm² (3.64mmtimes2.35mm) is designed to fully match 50-Omega input and output impedance. Under 8V and 2000mA dc bias condition, the PA deliver 38.1dBm (6.5W) saturated output power, 10.5-dB small signal gain and peak power added efficiency of 24.6% from 13.6 to 14.2GHz. This MMIC also achieved the best power densities (760mW/mm²) at Ku band reported to date     

测量大功率LDMOS晶体管特性的TRL校准方法研究

The impedance and output power measurements of LDMOS transistors are always a problem due to their low impedance and lead widths.An improved thru-reflect-line(TRL) calibration algorithm for measuring the characteristics of L-band high power LDMOS transistors is presented.According to the TRL algorithm,the individual two-port S parameters of each fixture half can be obtained.By de-embedding these S parameters of the test fixture,an accurate calibration can be made.The improved TRL calibration algorithm is successfully utilized to measure the characteristics of an L-band LDMOS transistor with a 90 mm gate width.The impedance of the transistor is obtained,and output power at 1 dB compression point can reach as much as 109.4 W at 1.2 GHz, achieving 1.2 W/mm power density.From the results,it is seen that the presented TRL calibration algorithm works well.     

High-performance 2 mm gate width GaN HEMTs on 6H-SiC with output power of 22.4 W @ 8 GHz

Optimized AlGaN/AlN/GaN high electron mobility transistors (HEMTs) structures were grown on 2-in. semi-insulating (SI) 6H-SiC substrate by metal–organic chemical vapor deposition (MOCVD). The 2-in. HEMT wafer exhibited a low average sheet resistance of 305.3 Ω/sq with a uniformity of 3.85%. The fabricated large periphery device with a dimension of 0.35 μm × 2 mm demonstrated high performance, with a maximum DC current density of 1360 mA/mm, a transconductance of 460 mS/mm, a breakdown voltage larger than 80 V, a current gain cut-off frequency of 24 GHz and a maximum oscillation frequency of 34 GHz. Under the condition of continuous-wave (CW) at 8 GHz, the device achieved 18.1 W output power with a power density of 9.05 W/mm and power-added-efficiency (PAE) of 36.4%. While the corresponding results of pulse condition at 8 GHz are 22.4 W output power with 11.2 W/mm power density and 45.3% PAE. These are the state-of-the-art power performance ever reported for this physical dimension of GaN HEMTs based on SiC substrate at 8 GHz.