多值逻辑基本运算的神经网络实现

多层感知器神经网络是典型的人工神经网络模型。算后，将其推广到多值逻辑。根据感知器神经元的分类特点，系统中的基本运算，从而也实现了任意三值逻辑函数。本文在分析二值感知器神经网络实现二值数字逻辑运采用三层前向稳健感知器神经网络实现了三值格代数。     

一种在二值计算机上实现多值逻辑运算的方法

分析了在二值计算机上实现多值逻辑运算与多值逻辑表示方法的关系，在此基础上，给出一种特殊多值逻辑值的二进制编码，并提出一种在二值计算机上建立起完备的多值逻辑运算集的方法，从而实现了在二值计算机上有效地解决实际多值逻辑问题。     

一种新的MOS电流型多值逻辑电路

本文提出了一种新的MOS电流型多值逻辑电路,并以十值逻辑为例,构成了完备多值逻辑系统所要求的各种十值电路。本文还研究了以这种多值逻辑电路构成实用系统的可能性。采用普通CMOS工艺制作的样品测试表明这种多值逻辑电路与其它多值逻辑电路相比,不仅具有完备的逻辑功能,而且具有集成度高,电路结构简单,易于实现和可靠性高的优点。     

任意值数的时序逻辑电路设计

本文提出了一种值数可任意扩展的多值逻辑存贮单元——DYL多值D触发器。文中将二值时序电路设计方法推广到多值逻辑系统中,运用DYL电路的线性与或门和阈门以及多值D触发器,实现了任意值数的时序逻辑电路设计。     

基于多值逻辑的模糊逻辑函数分析与综合

本文首先提出了模糊逻辑和多值逻辑的相似性，并从开关信号理论出发建立了多值逻辑阈运算和模糊函数取值区间有限等级的对应关系，进而提出了利用多值逻辑阈运算实现模糊逻辑函数分析与综合的算法，并用该算法对几个模糊逻辑函数实例进行了分析与综合，实例操作表明，该算法具有操作简单，规范，方便快捷的特点，是分析和综合模糊逻辑函数的有效方法。     

一种多值逻辑函数化简方法——决策树法

将决策树应用于多值逻辑函数的化简，提出了一种新的多值逻辑函数的化简方法，该方法易于编程和上机操作，特别适用于化简多变量的多值逻辑函数。     

多值逻辑函数Chrestenson谱的性质

类似于布尔函数Walsh谱的性质，本文得到了两个多值逻辑函数的和函数的Chrestenson循环谱等于这两个多值逻辑函数的Chrestenson循环谱的和的充分必要条件，以及两个多值逻辑函数的和函数的Chrestenson线性谱等于这两个多值逻辑函数的Chrestenson线性谱的和的充分条件。     

多值逻辑与电子科学技术(综述)

讨论了研究多值逻辑对发展电子科学技术的意义。从多值逻辑电路与多值数字系统逻辑设计以及多值逻辑应用诸方面综述了这个领域的发展概况与趋势。     

一种新型的MV-DYL电路多元逻辑(DYL)在多元逻辑应用中的新发展

以往科学家们总是以新器件的出现,及随之使整机产生了惊人的变化来划分计算机发展历史。然而一旦多值逻辑系统付诸实现,多值逻辑学说得到应用,这种高效率的计算机结构的出现,将可能使计算机技术进入更高的水平。我国DYL集成电路的发明为实现上述目标提供了新的希望。 本文指出,多元逻辑中的线性“与或”门本质上就是一种很好的多值逻辑“与或”门。它与其他电路配合可以构成一种新的多值逻辑电路(简称为MV-DYL)。通过比较和实验证明,MV-DYL电路在与二值DYL电路相同的功耗-时延积条件下,可以获得更高的信息密度。MV-DYL电路比三值CMOS和多值I~2L电路结构简单、容易制作和可靠性高。     

基于比较器的四值电流型CMOS加减电路设计

该文通过对电流型CMOS电路的阈值控制引入了多值电流型比较器。与2值逻辑电路相比,多值逻辑电路的单条导线允许更多的信息传输。相较于电压信号,电流信号易实现加、减等算术运算,在多值逻辑的设计上更加方便。同时提出了基于比较器的4值基本单元设计方法,实现了4值取大、取小以及反向器的设计,在此基础上设计实现了加法器和减法器。该设计方法在2值、3值以及n值逻辑上同样适用。实验结果表明所设计的电路具有正确的逻辑功能,较之相关文献电流型CMOS全加器有更低的功耗和更少的晶体管数。     

Non-binary functional synthesis using ACO-based heuristic

Multiple-valued logic (MVL) synthesis is a problem that has attracted increased interest in recent years. The MVL synthesis problem is more involved compared to its binary counterpart. The search space for finding optimal MVL functional synthesis is enormous. Conventional deterministic methods for MVL functional synthesis are prohibitively expensive, indicating an eminent need for the use of iterative heuristic-based synthesis techniques. In this paper, an ant colony optimization (ACO) based heuristic algorithm for synthesis of MVL functions is proposed. The algorithm mimics the ants' behaviour in the real world. Real ants are found to be able to select the shortest path between their nest and food sources in the existence of alternate paths, or even hurdles between the two. The proposed ACO algorithm uses some of the known real ant techniques in finding the shortest paths to the (near) optimal number of product terms that can cover the minterms of a given MVL function. The proposed algorithm is tested using 50 000 randomly generated 2-variable 4-valued functions. The results obtained using the proposed approach show that the proposed approach outperforms existing direct cover (DC) techniques in terms of the average number of product terms (implicants) required to synthesize a given MVL function.     

基于多值规则的知识表示及其应用

本文把多值逻辑引入专家系统中的知识表示,着重就模糊规则向多值规则的转换,二值规则和多值规则的混合表示,二值逻辑向多值逻辑的转换, 基于不同算子多值规则间的相互转换,以及采用管道结构从根本上解决专家系统中规则匹配速度慢等问题进行了研究,并首次将多值规则表示的知识用于电液位置伺服系统自适应律中的参数优化,进一步提高了控制器的性能.     

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.     

Ant colony optimisation–direct cover: a hybrid ant colony direct cover technique for multi-level synthesis of multiple-valued logic functions

The use of non-binary (multiple-valued) logic in the synthesis of digital systems can lead to savings in chip area. Advances in very large scale integration (VLSI) technology have enabled the successful implementation of multiple-valued logic (MVL) circuits. A number of heuristic algorithms for the synthesis of (near) minimal sum-of products (two-level) realisation of MVL functions have been reported in the literature. The direct cover (DC) technique is one such algorithm. The ant colony optimisation (ACO) algorithm is a meta-heuristic that uses constructive greediness to explore a large solution space in finding (near) optimal solutions. The ACO algorithm mimics the ant's behaviour in the real world in using the shortest path to reach food sources. We have previously introduced an ACO-based heuristic for the synthesis of two-level MVL functions. In this article, we introduce the ACO–DC hybrid technique for the synthesis of multi-level MVL functions. The basic idea is to use an ant to decompose a given MVL function into a number of levels and then synthesise each sub-function using a DC-based technique. The results obtained using the proposed approach are compared to those obtained using existing techniques reported in the literature. A benchmark set consisting of 50,000 randomly generated 2-variable 4-valued functions is used in the comparison. The results obtained using the proposed ACO–DC technique are shown to produce efficient realisation in terms of the average number of gates (as a measure of chip area) needed for the synthesis of a given MVL function.     

Higher radix linear sequential circuit implementation via hybrid U and JK multiple-valued logic primitives

The implementation of a 2-digit modulo-3 linear sequential circuit (LSC) is presented, together with its associated state diagram. Two multiple valued logic (MVL) primitives are identified as suitable building blocks for the realisation of the three basic elements required for higher radix (>2) LSC hardware. Specifically, the hybrid MVL combinational U-gate and the MVL sequential JK flipflop sequencer are identified as vehicles for the implementation of modulo-radix scalars, adders and delayers.<>     

SC and pass transistor combined circuits

The pass-transistor structure provides a powerful tool for the implementation of binary and multiple-valued logic (MVL). Circuit realisation of any general MVL function using literals, MAX and MIN is easy. However, the resulting circuits have certain limitations. A combination of pass transistors (PT) with switched-capacitor (SC) circuits is shown to provide useful improvements.<>     

A GaN/InGaN/AlGaN MQW RTD for versatile MVL applications with improved logic stability

To improve the logic stability of conventional multi-valued logic (MVL) circuits designed with a GaN-based resonate tunneling diode (RTD),we proposed a GaN/InGaN/AlGaN multi-quantum well (MQW) RTD.The proposed RTD was simulated through solving the coupled Schrodinger and Poisson equations in the numerical non-equilibrium Green's function (NEGF) method on the TCAD platform.The proposed RTD was grown layer by layer in epitaxial technologies.Simulated results indicate that its current-voltage characteristic appears to have a wider total negative differential resistance region than those of conventional ones and an obvious hysteresis loop at room temperature.To increase the Al composite of AlGaN barrier layers properly results in increasing of both the total negative differential resistance region width and the hysteresis loop width,which is helpful to improve the logic stability of MVL circuits.Moreover,the complement resonate tunneling transistor pair consisted of the proposed RTDs or the proposed RTD and enhanced mode HEMT controlled RTD is capable of generating versatile MVL modes at different supply voltages less than 3.3 V,which is very attractive for implementing more complex MVL function digital integrated circuits and systems with less devices,super high speed linear or nonlinear ADC and voltage sensors with a built-in super high speed ADC function.     

Multivalued logic integral calculus

In this paper, the concept of integration for Multi-Valued Logic (MVL) algebra is introduced and techniques for obtaining an MVL function whose desired changes are given in terms of changes in its arguments are developed. Two types of integrals, namely exact and compatible intergrals, are defined. The necessary and sufficient conditions for the existence of compatible integrals for a given differential expression and ways of realizing these integrals are presented here. Integral calculus has application in the design of an MVL digital system.     

RTD多值逻辑电路原理与电路模拟

由共振隧穿二极管(RTD)和高电子迁移率晶体管(HEMT)构成的多值逻辑(MVL)电路可以用最少的器件来完成一定的逻辑功能,达到大大简化电路的目的。共振隧穿二极管和高电子迁移率晶体管属于量子器件,具有高频高速的特点,所以这一逻辑电路有很好的应用前景。本文就多值逻辑电路中的几个典型电路用Pspice软件进行电路模拟,得到了与理论分析一致的模拟结果。