An efficient method for plasma-charging damage measurement

The initial slope of the voltage versus time curve during constant current stressing of gate-oxide has been demonstrated, for the first time, as a good indicator for plasma-charging damage. This method of damage measurement measures the charge trapping rate of the gate-oxide directly while it is under a high-field stress. It combines the stressing and measuring steps in one rapid measurement. Using only capacitors as testing vehicle, this method does not require extensive processing. Using current stressing instead of CV measurement, this method greatly reduces the measurement time and the size requirement of the capacitor. The ability of this measurement method in bringing out the passivated defects after annealing is demonstrated. An example of using this method in detecting plasma-charging damage is included     

Plasma process induced damage detection by fast wafer level reliability monitoring for automotive applications

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.     

Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed.     

A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

An evaluation of fast wafer level test methods for interconnect reliability control

A number of fast wafer level test methods exist for interconnect reliability evaluation. The relative abilities of three such methods to predict the quality and reliability of the interconnect over very short test times are evaluated in this work. Four different test structure designs are also evaluated and the results are compared with package level Median Time to Failure (MTF) results. The Isothermal test method combined with SWEAT-type test structures is shown to be the most suitable combination for interconnect reliability detection and control over very short times.     

A new wafer level reliability method for evaluation of ionic induced pmosfet drift effects

An ionic induced pMOSFET drift effect was investigated by deliberately enhancing the sodium concentration in interlevel dielectric layers.High frequency capacitance voltage and triangular voltage sweep (TVS) measurements as well as different bias temperature stress sequences were employed to show that the degradation is a two step process: sodium drift into active areas and charging of traps which were generated by sodium interactions with the semiconductor oxide interface.A special wafer level reliability method was developed which takes into consideration the two phase nature of the failure mechanism.     

A versatile, via terminated electromigration test structure for various stress modes used during fast wafer level reliability (fWLR) testing

A multipurpose electromigration (EM) test structure designed for advanced fast wafer level reliability (WLR) tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structures which is beneficial for early technology development as well as productive in-line monitoring. Highly accelerated WLR tests use the metal self-heating effect for temperature stress acceleration. It is shown here that the design of interconnects with respect to the critical metal line and the periphery of the tested metal line has a large impact on the stress temperature. A carefully designed test structure guarantees the ability to test for different EM failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.     

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.     

Fast electromigration wafer mapping for wafer fab process monitoring and improvement

In this work, a set up for fast wafer level electromigration (WL-EM) is developed with the use of a standard electrical analyser, a semi-auto probe station with a hot chuck, and a PC. EM tests on multiple test structures are carried out simultaneously and tests are done at multiple locations (EM mapping) across the wafer. Measured data are imported into MS EXCEL and analysed with a macro automatically. Good correlations are demonstrated between the fast WL-EM test and classical package level EM at 0.1% failure rate. For several years reliable EM monitoring charts are created with the fast WL-EM set up. The fast EM mapping test does not only exploit the advantages of fast WL-EM test in terms of short throughput time and low cost (without packaging) for process monitoring, the additional information on EM performance across the wafer makes the test extremely valuable for process improvement.     

A new method for on wafer noise measurement

A method for measuring the noise parameters of MESFETs and HEMTs is presented. It is based on the fact that three independent noise parameters are sufficient to fully describe the device noise performance. It is shown that two noise parameters, R_n and |Y_OPT|, can be directly obtained from the frequency variation of the noise figure F₅₀ corresponding to a 50 Ω generator impedance. By using a theoretical relation between the intrinsic noise sources as additional data, the F₅₀ measurement only can provide the four noise parameters. A good agreement with more conventional techniques is obtained     

Warpage simulation for the reconstituted wafer used in fan-out wafer level packaging

Fan-out packaging technology involves processing redistribution interconnects on reconstituted wafer, which takes the form of an array of silicon dies embedded in epoxy molding compound (EMC). Yields of the redistribution interconnect processes are significantly affected by the warpage of the reconstituted wafer. The warpage can be attributed to the crosslinking reaction and viscoelastic relaxation of the EMC, and to the thermal expansion mismatch between dissimilar materials during the reconstitution thermal processes. In this study, the coupled chemical-thermomechanical deformation mechanism of a commercial EMC was characterized and incorporated in a finite element model for considering the warpage evolution during the reconstitution thermal processes. Results of the analyses indicate that the warpage is strongly influenced by the volume percentage of Si in the reconstituted wafer and the viscoelastic relaxation of the EMC. On the other hand, contribution from the chemical shrinkage of the commercial EMC on warpage is insignificant. As such, evaluations based on the comprehensive chemical-thermomechanical model considering the full process history can be approximated by the estimations from a simplified viscoelastic warpage model considering only the thermal excursion.     

Emerging trend for LED wafer level packaging

Currently most light emitting diode (LED)components are made with individual chip packaging technology.The main manufacturing processes follow conventional chip-based IC packaging.In the past several y...     

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.     

Automated wafer level QBD measurement for production control

A novel technique is presented for the swift measurement of the charge necessary to induce failure in a thin SiO₂ film (QBD). This can form part of a powerful wafer-level reliability evaluation program through inclusion within an automated test system. The method is demonstrated by extracting the distribution of QBD values from across several 150-mm wafers     

Novel RF process monitoring test structure for silicon devices

This paper demonstrates a novel RFCMOS process monitoring test structure. Outstanding agreement in dc and radio frequency (RF) characteristics has been observed between conventional test structure and the new process monitoring test structure for MOSFET with good correlations in measured capacitances also noted for metal-insulator-metal capacitor and MOS varactor. Possible process monitoring test structure is also suggested as a reference benchmarking indicator for interconnects.     

用于圆片级封装的金凸点研制

介绍了电镀法进行圆片级封装中金凸点制作的工艺流程,并对影响凸点成型的主要工艺因素进行了研究.凸点下金属化层(UBM,under bump metallization)溅射、厚胶光刻和厚金电镀是其中的工艺难点,通过大量的实验研究,确定了TiW/Au的UBM体系,得到了优化的厚胶光刻工艺.同时,研制了用于圆片级封装金凸点制作的垂直喷镀设备,选用不同的电镀液体系和光刻胶体系,对电镀参数进行了控制和研究.对制作的金凸点与国外同类产品的基本特性进行了对比,表明其已经达到可应用水平.     

A narrow-band level set method applied to EIT in brain for cryosurgery monitoring

In this paper, we investigate the feasibility of applying a novel level set reconstruction technique to electrical imaging of the human brain. We focus particularly on the potential application of electrical impedance tomography (EIT) to cryosurgery monitoring. In this application, cancerous tissue is treated by a local freezing technique using a small needle-like cryosurgery probe. The interface between frozen and nonfrozen tissue can be expected to have a relatively high contrast in conductivity and we treat the inverse problem of locating and monitoring this interface during the treatment. A level set method is used as a powerful and flexible tool for tracking the propagating interfaces during the monitoring process. For calculating sensitivities and the Jacobian when deforming the interfaces we employ an adjoint formula rather than a direct differentiation technique. In particular, we are using a narrow-band technique for this procedure. This combination of an adjoint technique and a narrow-band technique for calculating Jacobians results in a computationally efficient and extremely fast method for solving the inverse problem. Moreover, due to the reduced number of unknowns in each step of the narrow-band approach compared to a pixel- or voxel-based technique, our reconstruction scheme tends to be much more stable. We demonstrate that our new method also outperforms its pixel-/voxel-based counterparts in terms of image quality in this application.     

A model and experiments for thin oxide damage from wafer chargingin magnetron plasmas

A physically based model that has been developed to explain the role of plasma nonuniformity in charge damage to oxides is presented. For a uniform plasma the local conduction currents to the water surface integrate to zero over the RF period, and the surface charging is sufficient to damage oxides. For the case of thin oxides under a gate exposed to a nonuniform magnetron plasma, the gate surface can charge up until the oxide tunneling current balances the difference in the mean local conduction currents from the plasma. It is this oxide current that leads to degradation. The oxide current obtained via SPICE circuit simulations, probe measurements and breakdown measurements shows good agreement with experimental damage data of `antenna' capacitors     

圆片级测试MEMS器件的解决之道

MEMS产业发展十分迅速,但是人们常常忽视对其的早期测试。乍一看来,MEMS器件和传统IC器件的制造十分相似,但是,由于MEMS器件具有额外的机械部分（大多是可活动的）和封装,这些部分的成本通常占其总成本的大部分,因此MEMS器件的特性比传统IC器件要复杂得多,而且各不相同。     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.