An efficient method for plasma-charging damage measurement

The initial slope of the voltage versus time curve during constant current stressing of gate-oxide has been demonstrated, for the first time, as a good indicator for plasma-charging damage. This method of damage measurement measures the charge trapping rate of the gate-oxide directly while it is under a high-field stress. It combines the stressing and measuring steps in one rapid measurement. Using only capacitors as testing vehicle, this method does not require extensive processing. Using current stressing instead of CV measurement, this method greatly reduces the measurement time and the size requirement of the capacitor. The ability of this measurement method in bringing out the passivated defects after annealing is demonstrated. An example of using this method in detecting plasma-charging damage is included     

Identification of plasma-induced damage conditions in VLSI designs

Typically, the plasma charging effect is investigated by using antenna test structures that do not replicate well enough conditions occurring in real VLSI integrated circuits (ICs). Consequently, understanding, modeling, and detection of plasma-charging-induced gate oxide damage in real IC's is often inadequate. This paper discusses a new plasma-charging monitoring technique that assesses the extent of the above problem. This technique employs a multiplexed antenna monitoring (MAM) test structure with 400+ antenna configurations to determine the dependency between IC layout and the extent of gate oxide damage. The paper reports the results of application of this technique to a 0.35-μm, 75-Å gate oxide, CMOS technology. The obtained results lead to a new definition of “antenna ratio” that is supposed to capture plasma-charging conditions in real VLSI circuits     

The impact of plasma-charging damage on the RF performance ofdeep-submicron MOSFET

Integration of RF analog functions with CMOS digital circuits offers great advantages in terms of cost and performance. Plasma-charging damage is known to degrade MOSFET characteristics and can be expected to impact the RF performance as well. In this work, we present for the first time a thorough investigation of the impact of plasma-charging damage on the RF characteristics of deep-submicron MOSFET. Our result shows that, with ultra-thin gate oxide, a 400°C forming gas annealing can completely recover the RF performance degradation due to plasma-charging damage     

Plasma-charging damage in ultra-thin gate oxide

The impact of plasma-charging damage on ultra-thin gate oxide is discussed. The argument for plasma-charging damage becoming less important is examined. Without considering the area and failure rate scaling effect, one mode of charging damage does become less important while other modes continue to be a serious problem. After scaling is properly accounted for, all charging damage remains a serious problem. The problem is more serious for thinner gate oxides because its life time becomes a limiting factor in device scaling. No one has yet made proper measurement for charging damage in the ultra-thin gate oxide regime. Stress-induced leakage current with properly designed tester may be used for ultra-thin gate-oxide damage measurement if one has the required sensitivity in the measurement. However, one must take care to use stress to reveal the latent defects that are hidden by annealing.     

Plasma-charging effects on submicron MOS devices

Plasma-charging damage on gate dielectrics of MOS devices is an important issue because of shrinking dimension, plasma nonuniformity, and effects on high-k gate dielectrics. A comprehensive study of plasma-charging effects on the electrical properties of MOS devices was investigated in this work. Shunt diodes were used to estimate the charging polarity distribution. For high-frequency application, the 1/f noise was found to be a promising index for assessing plasma-charging damage. Gate oxynitride formed by two-step nitridation was demonstrated to have better electrical reliability as compared to the conventional one-step nitridation, especially accompanied by amorphous silicon gate electrode. This improvement could be attributed to the relaxation of interface stress by amorphous silicon gate electrode and the suppression of hydrogen effects by gate oxynitride using two-step nitridation. Plasma-charging damage on Si₃N₄ and Ta₂O₅ gate dielectrics with high dielectric constant was also investigated. For MOS devices with Si₃N₄ film, the leakier characteristic and shorter time to breakdown reveal its inferior reliability. For MOS devices with Ta₂O₅ gate dielectric, the trap-assisted current mechanism makes a thicker physical thickness of Ta₂O₅ film more susceptible to plasma-charging-induced damage. Smaller physical thickness of Ta₂O₅ film in MOS devices is favorable due to the better reliability and comparable plasma-induced electrical degradation     

Damage to n-MOSFETs from electrical stress Relationship to processing damage and impact on device reliability

The study reported herein examines and compares damage to n-channel and p-channel metal-oxide-silicon field-effect transistors (MOSFETs) from direct current (d.c.) and alternating current (a.c.) electrical stresses as well as the relationship of this damage to plasma processing damage in MOSFETs. The lightly-doped drain (LDD) MOSFETs used are of 0.5 μm channel length and with a 90 Å thick thermally grown gate oxide fabricated using a full flow CMOS process up to and including metal-1 processes and post-metallization annealing (PMA). The damage to MOSFETs is assessed using transistor parameter characterization and charge-to-breakdown measurements on the gate oxide. It is found that manifestations of d.c. stress-induced damage and a.c. stress-induced damage to transistors are fairly similar in that both forms of damage are passivated by PMA and are reactivated by a subsequent d.c. electrical stress. However, a.c. stress-induced damage is observed to occur at much lower electric fields across the gate oxide than those necessary for d.c. stress-induced damage to be significant. This is attributed to a.c. currents, caused by carrier hopping, occurring at relatively low electric fields. One implication of our results is that plasma-charging damage, often attributed to d.c. electrical stress alone, may comprise an a.c. electrical stress component too.     

A New Technique for Measuring Gate-Oxide Leakage in Charging Protected MOSFETs

While accurate measurement of gate-oxide leakage in isolated CMOS oxides can be straightforward, it is not the case for CMOS oxides connected to a plasma-charging protection device. In this paper, a method enabling accurate gate-oxide leakage extraction from CMOS transistors directly connected to a gated MOSFET-based charging protection device is described. The method extracts gate-oxide leakage at the bottom side of the gate-oxide from the drain/source terminal of the protected MOSFETs biased into inversion while diverting the parasitic leakages from the protection device into a P⁺ tap sink. The location and design of the P⁺ tap sink play an important role on the success of the method. The method demonstrates a high measurement accuracy over the conventional method with a nearly 99% absorption efficiency of the protection-device-induced leakage by the P ⁺ tap sink, with the test structures used in this study. The method enables a saving of up to 30% of the layout space in the design of the charging test structures in test chips by eliminating usage of the fuse between the protected and protecting devices. A correlation study performed with the data measured by the new method and the conventional method suggests that both protected and protecting transistors can experience gate-oxide damage at the same time during back-end integrated circuit (IC) manufacturing process if the protected transistors violate the gate-charging design rules. It also indicates that the protected transistors have higher chance to receive more severe damage than the protecting transistors due to different oxide damage mechanisms associated with the terminal connectivity of these transistors     

Charging damage from plasma enhanced TEOS deposition

Serious n-channel transistor hot-carrier lifetime degradation due to plasma-charging damage during PETEOS deposition is reported for the first time. Contrary to conventional wisdom, a dielectric film thickness dependent damage is observed. A new mechanism for charging-damage during plasma deposition of dielectric is proposed. This new mechanism uses photoconduction to explain why the antennae continue to charge up after a layer of dielectric is deposited on top. Some numerical estimation is provided     

基于LS-SVM的压电智能结构损伤主动监测

基于被动监测技术的局限性,搭建了损伤主动监测系统,对监测信号进行了功率谱密度最大值(PSM)特征提取,并提出了一种基于最小二乘支持向量机(LS-SVM)的损伤检测方法。采用该方法,对压电智能复合材料层板进行了损伤定位的研究,并与改进的BP网络进行了对比,结果表明:在相同性能指标下,LS-SVM有比BP网络更高的损伤定位精度及更强的泛化能力。LS-SVM与主动监测技术的融合,为结构实现在线实时准确监测提供了一种新途径。     

A new method for detecting electromigration failure in VLSI metallization

A method has been developed for metallization lifetime predictions using a continuous resistance monitoring technique. A useful lifetime criteria, based upon measured resistance changes, has been determined that is more sensitive and, consequently, more accurate than present catastrophic failure techniques.     

Evaluation of subcell power conversion efficiencies of radiation‐damaged triple‐junction solar cells using photoluminescence decays

We characterize the radiation‐induced damage of InGaP/GaAs/Ge solar cells for various proton irradiation energies and fluences using conventional current‐voltage (I‐V) measurements, external quantum efficiency, and a noncontact time‐resolved photoluminescence (PL) technique. From the I‐V curves, we obtain the conversion efficiency of the entire device. The external quantum efficiency showed that the short‐circuit current is only determined by the top InGaP subcell. To obtain accurate information about the point of maximum power, a new PL technique is introduced. The PL time decays of the InGaP and GaAs subcells are measured to obtain the characteristic decay time constants of carrier separation and recombination. We empirically verify that the time‐resolved PL method can be used to predict the electrical conversion efficiency of the subcells. We find that the limiting subcell at the point of maximum power is different from that for short‐circuit current. Radiation damage in unexpected regions of the device is revealed using this optical method.     

通过直接栅电流测量研究PMOSFET's热载流子损伤

通过直接栅电流测量方法研究了热载流子退化和高栅压退火过程中PMOSFET's热载流子损伤的生长规律.由此,给出了热载流子引起PMOSFET's器件参数退化的准确物理解释.并证明了直接栅电流测量是一种很好的研究器件损伤生长和器件参数退化的实验方法.     

Current-Based Testing,Modeling and Monitoring for Operational Deterioration of a Memristor-Based LUT

This paper presents a method for operational testing of a memristor-based look-up table (LUT) memory block. In the proposed method the deterioration of the memristors (as storage elements of a LUT), is modeled based on the reduction of the resistance range, a phenomenon well known as reported in the technical literature. A quiescent current technique is used to diagnose the memristors when deterioration results in a change of state, thus leading to a fault. In addition to testing, the proposed method can be utilized also for continuous monitoring of the memristor deterioration in the LUT. The deterioration of the memristors is modeled using a simple yet accurate equivalent circuit. The proposed method is simulated using LTSPICE and extensive simulation results are presented for operational deterioration with respect to different features such as LUT dimension, range of memristance and MOSFET feature size. These results show that the proposed test method is highly efficient for testing and monitoring a LUT in the presence of deteriorating multiple memristors.     

Accurate determination of ultrathin gate oxide thickness andeffective polysilicon doping of CMOS devices

We present an efficient and accurate method to characterize the physical thickness of ultrathin gate oxides (down to 25 Å) and the effective polysilicon doping of advanced CMOS devices. The method is based on the model for Fowler-Nordheim (F-N) tunneling current across the gate oxide with correction in gate voltage to account for the polysilicon-gate depletion. By fitting the model to measured data, both the gate oxide thickness and the effective poly doping are unambiguously determined. Unlike the traditional capacitance-voltage (C-V) technique that overestimates thin-oxide thickness and requires large area capacitor, this approach results in true physical thickness and the measurement can be performed on a standard sub-half micron transistor. The method is suitable for oxide thickness monitoring in manufacturing environments     

Hot-carrier-induced degradation of LDD polysilicon TFTs

In order to improve the stability of polysilicon thin-film transistors (TFTs) several drain junction architectures have been proposed. In this paper, the hot-carrier (HC) related stability of the lightly doped drain (LDD) TFT architecture is analyzed by using an iterative algorithm that relates the HC induced damage to the carrier injection across the device interfaces with gate and substrate oxide. The resulting creation of interface states and trapped charge is taken into account by using a system of rate equations that implements mathematically the Lais two step model, in which the generation of interface states is attributed to the trapping of hot-holes by centres into the oxide followed by the recombination with hot electrons. The rate equations are solved self-consistently with the aid of a device simulation program. By successive iterations, the time evolution of the interface state density and positive trapped charge distribution has been reconstructed, and the electrical characteristics calculated with this model are in good agreement with experimental data. This algorithm represent an improvement of an already proposed degradation model, in which the interface states formation dynamics is accounted by using a phenomenological approach. The present model has been applied to reproduce the degradation pattern of LDD TFTs and it is found that generation of interface states proceed almost symmetrically on the front and back device interfaces, starting from the points in which the transverse electric field peaks, and moving toward the drain side of the device. The final interface states distribution determines a sort of "bottleneck" in the active layer carrier density, that can explain the sensitivity to HC induced damage of both transfer and output characteristics.     

ESR and capacitance monitoring of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier

Condition monitoring plays an important role in estimating health condition of capacitors because the ageing of the capacitors is usually accompanied by an increase in equivalent series resistance (ESR) and a decrease in capacitance. Either capacitance or ESR cannot be a unique indicator of the lifetime of capacitors in some cases. This paper presents a condition monitoring method of a dc-link capacitor used in a three-phase PWM inverter with a front-end diode rectifier intended for motor drives. The monitoring method extracts both the ESR and capacitance of a capacitor under test from the actual ripple current and voltage without disconnecting the capacitor nor injecting an additional current. The monitoring method, therefore, can be implemented online. Experimental results verify that the monitoring method independently obtains the ESR and capacitance changes of the capacitor under test. This contributes to accurate lifetime estimation of dc-link capacitors.     

Implementation of BIC monitor in balanced analogue self-test

The authors present the design of a dynamic built-in current (BIC) monitor for a new on-chip analogue self-test methodology. This methodology uses dynamic power supply current monitoring, and takes advantage of a redundancy in the structure of fully balanced circuits. The dynamic BIC monitor is based on a second generation current conveyor CCII+, and offers accurate measurement of supply current with minimal degradation in power supply voltage     

An integrated healthcare system for personalized chronic disease care in home-hospital environments

Facing the increasing demands and challenges in the area of chronic disease care, various studies on the healthcare system which can, whenever and wherever, extract and process patient data have been conducted. Chronic diseases are the long-term diseases and require the processes of the real-time monitoring, multidimensional quantitative analysis, and the classification of patients' diagnostic information. A healthcare system for chronic diseases is characterized as an at-hospital and at-home service according to a targeted environment. Both services basically aim to provide patients with accurate diagnoses of disease by monitoring a variety of physical states with a number of monitoring methods, but there are differences between home and hospital environments, and the different characteristics should be considered in order to provide more accurate diagnoses for patients, especially, patients having chronic diseases. In this paper, we propose a patient status classification method for effectively identifying and classifying chronic diseases and show the validity of the proposed method. Furthermore, we present a new healthcare system architecture that integrates the at-home and at-hospital environment and discuss the applicability of the architecture using practical target services.     

IoT-based low-cost prototype for online monitoring of maximum output power of domestic photovoltaic systems

This paper presents a low-cost prototype for monitoring online the maximum power produced by a domestic photovoltaic (PV) system using Internet of Things (IoT) technology. The most common tracking algorithms (P&O, InCond, HC, VSS InCond, and FL) were first simulated using MATLAB/Simulink and then implemented in a low-cost microcontroller (Arduino). The current, voltage, load current, load voltage, power at the maximum power point, duty cycle, module temperature, and in-plane solar irradiance are monitored. Using IoT technology, users can check in real time the change in power produced by their installation anywhere and anytime without additional effort or cost. The designed prototype is suitable for domestic PV applications, particularly at remote sites. It can also help users check online whether any abnormality has happened in their system based simply on the variation in the produced maximum power. Experimental results show that the system performs well. Moreover, the prototype is easy to implement, low in cost, saves time, and minimizes human effort. The developed monitoring system could be extended by integrating fault detection and diagnosis algorithms.     

天线效应对LPNP管输出曲线的影响

天线结构是监控半导体工艺过程中等离子体损伤的一种典型结构,一般主要用来监控MOS器件栅氧的损伤。文中,该结构用来监控横向PNP(LPNP)管工艺过程中的发射极结损伤。实验发现,带天线结构的LPNP管的输出曲线容易出现翘曲现象,分析认为该异常不是由于发射极结损伤造成的,因为发射极结工艺过程中并没有受到损伤。同时发现该翘曲现象在LPNP管保护环接低电位时会消失,该低电位在很大范围内变化时,输出曲线基本一致,且输出曲线电流较保护环悬空时的电流整体偏大,在集电极电压较大时,输出电流和保护环悬空时的电流一致。