Decoupling the Bias‐Stress‐Induced Charge Trapping in Semiconductors and Gate‐Dielectrics of Organic Transistors Using a Double Stretched‐Exponential Formula

A novel strategy for analyzing bias‐stress effects in organic field‐effect transistors (OFETs) based on a four‐parameter double stretched‐exponential formula is reported. The formula is obtained by modifying a traditional single stretched‐exponential expression comprising two parameters (a characteristic time and a stretched‐exponential factor) that describe the bias‐stress effects. The expression yields two characteristic times and two stretched‐exponential factors, thereby separating out the contributions due to charge trapping events in the semiconductor layer‐side of the interface and the gate‐dielectric layer‐side of the interface. The validity of this method was tested by designing two model systems in which the physical properties of the semiconductor layer and the gate‐dielectric layer were varied systematically. It was found that the gate‐dielectric layer, in general, plays a more critical role than the semiconductor layer in the bias‐stress effects, possibly due to the wider distribution of the activation energy for charge trapping. Furthermore, the presence of a self‐assembled monolayer further widens the distribution of the activation energy for charge trapping in gate‐dielectric layer‐side of the interface and causes the channel current to decay rapidly in the early stages. The novel analysis method presented here enhances our understanding of charge trapping and provides rational guidelines for developing efficient OFETs with high performance.     

Monitoring the Channel Formation in Organic Field‐Effect Transistors via Photoinduced Charge Transfer

Conducting channel formation in organic field‐effect transistors (OFETs) is considered to happen in the organic semiconductor layer very close to the interface with the gate dielectric. In the gradual channel approximation, the local density of accumulated charge carriers varies as a result of applied gate bias, with the majority of the charge carriers being localized in the first few semiconductor monolayers close to the dielectric interface. In this report, a new concept is employed which enables the accumulation of charge carriers in the channel by photoinduced charge transfer. An OFET employing C₆₀ as a semiconductor and divinyltetramethyldisiloxane‐bis(benzocyclobutene) as the gate dielectric is modified by a very thin noncontinuous layer of zinc‐phthalocyanine (ZnPc) at the semiconductor/dielectric interface. With this device geometry, it is possible to excite the phthalocyanine selectively and photogenerate charges directly at the semiconductor/dielectric interface via photoinduced electron transfer from ZnPc onto C₆₀. Thus the formation of a gate induced and a photoinduced channel in the same device can be correlated.     

Oxygen vacancies in high-k oxides

High dielectric constant (K) gate oxides such as HfO₂ have suffered from charge trapping, threshold voltage shifts and a difficulty of metal or poly-Si gates to achieve band edge work function values. We investigate how these are related to the oxygen vacancies in a series of ab-initio calculations. The O vacancy is found to correlate with optical, luminescence and charge pumping spectra. The O vacancy contributes to the Fermi level pinning effect, which limits the band edge work functions. Inhibiting motion of vacancies may allow less pinning of gate electrode work functions.     

Novel gate voltage ramping technique for the characterisation of metal-oxide-semiconductor capacitor charge trapping properties

A novel technique is proposed to characterise the charge trapping properties of MOS capacitors by using the gate voltage ramping test. The parameter I=1-I/sub g/(t)/I/sub s/(t+ Delta t) measured during gate voltage ramping reveals the dielectric charge trapping characteristics. Positive charge trapping before dielectric breakdown was observed using this technique. A comparison between I and flatband voltage shift, Delta V/sub fb/, indicates that I gives the same information as Delta V/sub fb/ does at high stress fluences.<>     

Investigation of turn-on voltage shift in organic ferroelectric transistor with high polarity gate dielectric

Large positive shifts of turn-on voltage V_to were observed in ferroelectric organic thin film transistor using P(VDF-TrFE) copolymer (57–43 mol%) as gate insulator during OFF to ON state sweeping. The shift of the transfer characteristic up to +25 V is attributed to the accumulation of mobile charge carriers (holes) in pentacene layer even during the device OFF state. The observed phenomena were first discussed on the basis of a negative surface potential created by the dipole field of a polar dielectric and trap states in an organic semiconductor layer. It was however found that these were unable to fully address the observed strong V_to shift due to the presence of large polarization in the P(VDF-TrFE) layer. A mechanism of negative polarization-compensating charges which are injected to the insulator region next to the semiconductor layer was proposed and examined to understand the phenomenon. The turn-on voltage is found to change with different magnitude of positive voltage pulses, and corresponds to different amount of charges injected for compensation. Time measurement of drain current shows a transient decaying behavior when gate bias is switched from positive to negative polarity which confirms the trapping of negative charges in the insulator.     

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (V_th) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the V_th shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer.     

Nitrogen Plasma Processing of SiO2/4H-SiC Interfaces

A nitrogen plasma annealing process for gate dielectric applications in 4H-SiC metal oxide semiconductor (MOS) technology has been investigated. This process results in substantially greater interfacial N coverage at the SiO₂/4H-SiC interface and lower interface trap densities than the state-of-the-art nitric oxide (NO) annealing process. Despite these exciting results, the field-effect mobility of MOS field-effect transistors (MOSFETs) fabricated by use of this process is very similar to that of NO-annealed MOSFETs. These results emphasize the importance of understanding mobility-limiting mechanisms in addition to charge trapping in next-generation 4H-SiC MOSFETs.     

Charge trapping and reliability characteristics of ultra-thin HfYOx films on n-GaAs substrates

Ultra-thin layers of the HfYO_x gate dielectric were deposited on n-GaAs substrates by employing radio frequency (rf) sputter deposition system with a Si interface control layer sandwiched between the dielectric and semiconductor. The trapping/detrapping behaviour of charge carriers in the ultra-thin HfYO_x/Si gate dielectric stack has been extensively studied during constant-voltage stressing (CVS) and compared with the results obtained from directly deposited HfYO_x films on n-GaAs. The increase in gate leakage current observed during electrical stress is estimated and explained by taking into account the build up of trap charges and stress induced trap generation. Also, the capture cross-section of the generated traps is estimated. The variation of the trap centroid and the trapped charge density with injected influences have been investigated using constant current stressing (CCS) measurements. The dielectric breakdown and reliability of the dielectric films have been studied using constant-voltage stressing. A high time-dependent dielectric breakdown (TDDB, t_bd  1700 s) is observed for HfYO_x gate dielectric with a silicon inter-layer under a high constant-voltage stress (8 V).     

A fast measurement technique of MOSFETI/sub d/-V/sub g/ characteristics

In this letter, we developed an improved ultrafast measurement method for threshold voltage V/sub th/ measurement of MOSFETs. We demonstrate I/sub d/--V/sub g/ curve measurement within 1 /spl mu/s to extract the threshold voltage of MOSFET. Errors arising from MOSFET parasitics and measurement setup are analyzed quantitatatively. The ultrafast V/sub th/ measurement is highly needed in the investigation of gate dielectric charge trapping effect when traps with short detrapping time constants are present. Application in charge trapping measurement on HfO/sub 2/ gate dielectric is demonstrated.     

Gate pulse electrical method to characterize hysteresis phenomena in organic field effect transistor

Hysteresis phenomena in the current–voltage characteristics of organic thin-film transistors (OTFTs) between the up and down sweeps are commonly observed. This hysteresis behavior is strongly affected by the trapping-effect. In this work, we present a new experimental technique to study these phenomena. The technique is based on the time-dependent drain current measurements as a function of a pulsed gate voltage. The decay of the drain current observed when a gate bias is applied to the gate electrode is correlated to the trapping-detrapping effects in the silicon oxide and/or at the organic semiconductor/silicon oxide interface. We show how to use this pulse gate electrical method to characterize the true device performances (threshold voltage, carrier mobility) of petacene organic field effect transistors (OFETs) with SiO₂ gate dielectric under different pulsed conditions, avoiding the pitfalls due to the presence of the hysteresis effect when using classical static data analysis methods. Moreover, we demonstrate that the charge carrier mobility is less affected by the trapping and detrapping phenomena than the threshold voltage.     

Dual work function metal gate CMOS transistors by Ni-Tiinterdiffusion

In this letter, we present dual work function metal gate complementary metal-oxide semiconductor (CMOS) transistors with thin SiO ₂ gate dielectric fabricated through the interdiffusion of nickel and titanium. The threshold voltage of the n-MOS devices is determined solely by Ti, while the threshold voltage of the p-MOS devices is determined by the Ni-rich alloy of Ti and Ni. The advantage of this new approach is that low threshold voltages for surface-channel n-MOS and p-MOS transistors can be achieved simultaneously. At the same time, the integrity of the gate dielectric is preserved since no metal has to be etched from the surface of the gate dielectric. With gate depletion eliminated, these transistors exhibit high inversion charge and drive current     

Enhancement of Carrier Mobilities of Organic Semiconductors on Sol–Gel Dielectrics: Investigations of Molecular Organization and Interfacial Chemistry Effects

The dielectric‐semiconductor interfacial interactions critically influence the morphology and molecular ordering of the organic semiconductor molecules, and hence have a profound influence on mobility, threshold voltage, and other vital device characteristics of organic field‐effect transistors. In this study, p‐channel small molecule/polymer (evaporated pentacene and spin‐coated poly(3,3?;‐didodecylquarterthiophene) – PQT) and n‐channel fullerene derivative ({6}‐1‐(3‐(2‐thienylethoxycarbonyl)‐propyl)‐{5}‐1‐phenyl‐[5,6]‐C61 – TEPP‐C61) show a significant enhancement in device mobilities ranging from ～6 to ～45 times higher for all classes of semiconductors deposited on sol–gel silica gate‐dielectric than on pristine/octyltrichlorosilane (OTS)‐treated thermally grown silica. Atomic force microscopy, synchrotron X‐ray diffraction, photoluminescence/absorption, and Raman spectroscopy studies provide comprehensive evidences that sol–gel silica dielectrics‐induced enhancement in both p‐ and n‐channel organic semiconductors is attributable to better molecular ordering/packing, and hence reduced charge trapping centers due to lesser structural defects at the dielectric‐semiconductor interface.     

Gate bias polarity dependence of charge trapping and time-dependentdielectric breakdown in nitrided and reoxidized nitrided oxides

The gate bias polarity dependence of charge trapping and time-dependent dielectric breakdown (TDDB) in nitrided and reoxidized nitrided silicon dioxides prepared by rapid thermal processing (RTP) is reported. Charge trapping during high-field injection can be reduced by rapid thermal nitridation for both substrate and gate injection. While reoxidation of nitrided oxides shows further reduction in charge trapping for substrate injection, degradation is observed for gate injection. Similar effects are observed for TDDB: reoxidized nitrided oxides show charge-to-breakdown in excess of 300 C/cm² for substrate injection, but less than 30 C/cm² for gate injection. These effects are related to the nitrogen and hydrogen profiles in the oxides. By tailoring the process conditions, a symmetric behavior of NO and RONO films with low charge trappings and Q _BD in excess of 50 C/cm² is possible, making them attractive as long-lifetime dielectrics from EEPROM (electrically erasable programmable ROM) and flash EEPROM technologies     

The mutual influence of surface energy and substrate temperature on the saturation mobility in organic semiconductors

We report on a mutual correlation between the substrate temperature during semiconductor deposition and the surface energy of the gate dielectric on the charge carrier mobility in bottom gate top contact organic field effect transistors (OFETs) with N,N′-diphenyl-3,4,9,10-perylene tetracarboxylic diimide (DP-PDI) as organic semiconductor.     

Charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

Fabrication and characterization of 4H-SiC planar MESFETs

The planar 4H-SiC MESFETs were fabricated by employing an ion-implantation process instead of a recess gate etching process, which is commonly adapted in compound semiconductor MESFETs, to eliminate potential damage to the gate region during etching process. Excellent ohmic and Schottky contact properties were achieved by using the modified RCA cleaning of 4H-SiC surface and the sacrificial thermal oxide layer. The fabricated MESFETs was also free from drain current instability, which the most of SiC MESFETs have been reported to suffer for the charge trapping. The drain current recovery characteristics were also improved by passivating the surface with a thermal oxide layer and eliminating the charge trapping at the surface. The performance of fabricated MESFETs was characterized by analyzing the small-signal equivalent circuit parameters extracted from the measured parameters.     

Modelling negative bias temperature instabilities in advanced p-MOSFETs

The decrease of the threshold voltage V_th of p-channel metal-oxide semiconductor field effect transistors (p-MOSFET) with ultrathin gate dielectric layers under negative bias temperature stress is studied. A degradation model is developed, that accounts for the generation of Si₃Si^√ (P_b0) centers and bulk oxide defects, induced by the tunnelling of electrons or holes through the gate dielectric layer during the electrical stress. The model predicts that V_th shifts are mainly due to the tunnelling of holes at low gate bias |V_G|, typically below 1.5 V, while electrons are mainly responsible for these shifts at higher |V_G|. Consequently, device lifetime at operating voltage, based on V_th shifts, should not be extrapolated from measurements performed at high gate bias. The impact of nitrogen incorporated at the Si/dielectric interface on V_th shifts is next investigated. The acceleration of device degradation when the amount of nitrogen increases is attributed to the increase in local interfacial strain, induced by the increase in bonding constraints, as well as to the increase in the density of Si---N---Si strained bonds, that act as trapping centers of hydrogen species released during the electrical stress. Finally, V_th shifts in p-MOSFET with Hf_ySiO_x gate layers and SiO₂/Hf_ySiO_x gate stacks are simulated, taking into account the generation of P_b0 centers induced by the injection of electrons through the structure. It is found that the transistor lifetime, based on threshold voltage shifts, is improved in SiO₂/Hf_ySiO_x gate stacks as compared to single Hf_ySiO_x layers. This finding is attributed to the beneficial presence of the SiO₂ interfacial layer, which allows the relaxation of strain at the Si/dielectric interface.