Examination of the time power law dependencies in hot carrierstressing of n-MOS transistors

The origins of the different power laws arising from hot carrier stressing at low and high gate voltages are examined. It is found that damage at V_g=V_d (predominantly electron trapping in the oxide) has the same underlying 0.5 power law exponent dependence as stress under I_b(max) (interface state creation) conditions, if degradation is measured as a function of injected electronic charge instead of time. It is proposed that the reduced gradient normally seen under V_g=V_d stresses arises due to the repulsive electrostatic oxide fields created by the trapped oxide charge and does not reflect the fundamental rate of trap creation. Stressing at low gate voltages (V_g=V_d/5) also reveals the presence of a similar time power law of exponent 0.5 when the oxide trap contribution alone is separated out from the rest of the damage. It is concluded that the 0.5 power law appears to be the fundamental underlying kinetic equation that is seen throughout the gate voltage stress range, despite the different types of damage and the very different trap creation mechanisms     

Hot-carrier-induced degradation in short p-channel nonhydrogenatedpolysilicon thin-film transistors

The effects of low gate voltage |V_g| stress (V_g =-2.5 V, V_d=-12 V) and high gate voltage |V_g| stress (V_g=V_d=-12 V) on the stability of short p-channel nonhydrogenated polysilicon TFTs were studied. The degradation mechanisms were identified from the evolution with stress time of the static device parameters and the low-frequency drain current noise spectral density. After low |V_g| stress, transconductance overshoot, kinks in the transfer characteristics, and positive threshold voltage shift were observed. Hot-electron trapping in the gate oxide near the drain end and generation of donor-type interface deep states in the channel region are the dominant degradation mechanisms. After high |V_g| stress, transconductance overshoot and "turn-over" behavior in the threshold voltage were observed. Hot-electron trapping near the drain junction dominates during the initial stages of stress, while channel holes are injected into the gate oxide followed by interface band-tail states generation as the stress proceeds     

Effect of Floating-Body and Stress Bias on NBTI and HCI on 65-nm SOI pMOSFETs

Grounded-body (GB) core-logic/high-speed (HS) and input/output (I/O) silicon-on-insulator pMOSFETs from 65-nm technology are shown to degrade more than floating-body (FB) devices under negative bias temperature instability (NBTI) stress. However, in both cases, worst case degradation occurs when stressed under equal gate and drain voltages (V_g = V_d), whereby degradation is simultaneously induced by both NBTI and hot carrier injection (HCI) simultaneously ("concurrent HCI-NBTI"), the relative importance of each mechanism depending on the type of device and the bias level. The degradation of I/O pMOSFETs stressed under V_g = V_d at room temperature shows predominantly NBTI-like behavior at higher stress voltages, whereas it shows concurrent HCI-NBTI behavior at lower stress voltages. By contrast, the degradation of HS pMOSFETs stressed under V_g = V_d shows concurrent HCI-NBTI behavior over the entire stress bias range. In both cases, FB devices degrade more than GB devices for higher stress voltage values, but the FB effects weaken and the degradations become comparable for lower stress bias.     

Hot-carrier effects and reliable lifetime prediction in deepsubmicron N- and P-channel SOI MOSFETs

Hot-carrier effects are thoroughly investigated in deep submicron N- and P-channel SOI MOSFETs, for gate lengths ranging from 0.4 μm down to 0.1 μm. The hot-carrier-induced device degradations are analyzed using systematic stress experiments with three main types of hot-carrier injections-maximum gate current (V_g≈V_d ), maximum substrate current (V_g≈V_d/2) and parasitic bipolar transistor (PBT) action (V_g≈0). A two-stage hot-carrier degradation is clearly observed for all the biasing conditions, for both N- and P-channel devices and for all the gate lengths. A quasi-identical threshold value between the power time dependence and the logarithmic time dependence is also highlighted for all the stress drain biases for a given channel length. These new findings allow us to propose a reliable method for lifetime prediction using accurate time dependence of degradation in a wide gate length range     

A unified model for the self-limiting hot-carrier degradation inLDD n-MOSFETs

A new insight into the self-limiting hot-carrier degradation in lightly-doped drain (LDD) n-MOSFETs is presented. The proposed model is based on the charge pumping (CP) measurement. By progressively lowering the gate base level, the channel accumulation layer is caused to advance into the LDD gate-drain overlap and spacer oxide regions, extending the interface that can be probed. This forms the basis of a novel technique, that allows the contributions to the CP current, due to stress-induced interface states in the respective regions, to be effectively separated. Results show that interface state generation initiates in the spacer oxide region and progresses rapidly into the overlap/channel region with stress time. The close correspondence between the linear drain current degradation, measured at high and low gate bias, and the respective interface state generation in the spacer and the overlap/channel regions deduced from CP data, provides an unambiguous experimental evidence that the degradation proceeds in a two-stage mechanism, involving first a series resistance increase and saturation, followed by a carrier mobility reduction. The saturation in series resistance increase results directly from a reduced interface state generation rate in the spacer oxide. For a given density of defect precursors and considering an almost constant channel field distribution near the drain region during stress, interface trap generation rate is shown to exhibit an exponential stress time dependence, with a characteristic time constant determined by the applied voltages. This observation leads to a lifetime extrapolation methodology. Lifetime due to a particular stress drain voltage V_d, may be extracted from a single composite degradation characteristic, obtained by shifting characteristics for various stress V_d's, along the stress time axis, until the characteristics merge into a single curve     

Determination of interface trap capture cross sections usingthree-level charge pumping

A modified three-voltage-level charge pumping (CP) technique is described for measuring interface trap parameters in MOSFETs. Charge pumping (CP) is a technique for studying traps at the Si-SiO₂ interface in MOS transistors. In the CP technique, a pulse is applied to the gate of the MOSFET which alternately fills the traps with electrons and holes, thereby causing a recombination current I_cp to flow in the substrate. With this technique, interface trap capture cross sections for both electrons and holes may be determined as a function of trap energy in a single device. It is demonstrated that a modified three-level charge pumping method may be used to determine not only interface trap densities but also to capture cross sections as a function of trap energy. The trap parameters are obtained for both electrons and holes using a single MOSFET     

Charge trap generation in LPCVD oxides under high field stressing

The degradation of low pressure chemical vapor deposited (LPCVD) oxides, prepared using silane and tetra ethyl ortho silicate (TEOS) as the source, has been investigated under high field stressing. The LPCVD oxides exhibit enhanced conductivity for the Fowler-Nordheim tunneling current, which is modeled as an effective lowering of potential barrier at the injecting electrode. The charge to breakdown (Q_bd) of LPCVD oxides depends on both the deposition chemistry and post deposition annealing condition. The change in interface-state density (ΔD_it), flatband voltage (ΔV_fb), and gate voltage (Δ|V_g|) during constant current stressing are studied to identify the degradation mechanism. We see a very good correlation between Q_bd and Δ|V_g|, indicating that the degradation in LPCVD oxides is dominated by bulk trap generation and subsequent charge trapping. We present a detailed theoretical analysis to substantiate this     

Behavior of substrate enhanced electron injection in advanced deep sub-micron NMOSFETs

Hot carrier degradation under conventional maximum substrate current I_b,max, electronic gate current I_g (HE) and substrate enhanced electron injection (SEEI) in advanced deep sub-micron NMOSFETs is studied. It is found that the interface trap generation is the dominant mechanism for hot carrier degradation under these three stress conditions. Furthermore, the behavior of SEEI under AC stress applied to the gate is investigated by charge pumping. The results indicate that the interface trap generation is also the dominant mechanism for hot carrier degradation under AC stress. However, due to the recovery of SEEI, the degradation of the electrical parameters for NMOSFETs at equally effective stress duration under AC stress is slightly less than that under DC stress. Finally, the recovery behavior of secondary impact ionization damage is discussed by using an on-the-fly technique and the charge pumping spot measurement technique. It is found that the passivation of the interface traps is directly responsible for the recovery of I_dlin.     

Study of low-frequency charge pumping on thin stacked dielectrics

The application of low-frequency charge pumping to obtain near-interface, or bulk trap densities, on thin stacked gate dielectrics is studied. A review of the theory governing the low-frequency charge pumping technique, developed to extract bulk trap densities from metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated with thick SiO₂ dielectrics, is given. In this study, the technique is applied to a series of n-channel MOSFETs fabricated with stacked gate dielectrics. The dielectric stacks were comprised of rapid thermal oxide (RTO) interface layers and rapid thermal chemical vapor deposited (RTCVD) oxynitride layers, which incorporated varying concentrations of nitrogen. The effect of DC tunneling currents on the technique is studied, and a procedure to remove these components from the measured substrate current is outlined. Distortions in the experimentally measured charge pumping current plotted as a function of gate bias is modeled and found to be due to the contribution of bulk traps. Finally, the limitations of applying a model that was originally developed for thick SiO₂ dielectrics to thin stacked gate dielectrics are discussed     

Reconciliation of different gate-voltage dependencies of 1/f noisein n-MOS and p-MOS transistors

We have examined the 1/f noise of 3 μm×16 μm, n- and p-MOS transistors as a function of frequency (f), gate-voltage (V_g ) and temperature (T). Measurements were performed for 3 Hz⩽f⩽50 kHz, 100 mV⩽|V_g-V_th|⩽4 V, and 77 K⩽T⩽300 K, where V_th is the threshold voltage. Devices were operated in strong inversion in their linear regimes. At room temperature we find that, for n-MOS transistors, S(V_d)∝V_d²/(V_g-V_th )², and for p-MOS transistors, we generally find that S(V_d)∝V_d²/(V_g-V_th , consistent with trends reported by others. At lower temperatures, however, the results can be very different. In fact, we find that the temperature dependence of the noise and the gate-voltage dependence of the noise show similar features, consistent with the idea that the noise at a given T and V_g is determined by the trap density, D_t(E), at trap energies E=E(T,V_g). Both the T- and V_g-dependencies of the noise imply that D_t (E) tends to be constant near the silicon conduction band edge, but increases as E approaches the valence band edge. It is evidently these differences in D_t(E) that lead to differences in the gate-voltage dependence of the noise commonly observed at room temperature for n- and p-MOS transistors     

Effects of hot carrier induced interface state generation insubmicron LDD MOSFET's

A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 μm LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V_g ≃0.5 V_d in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states     

Separation of hot-carrier-induced interface trap creation and oxidecharge trapping in PMOSFETs studied by hydrogen/deuterium isotope effect

By using the hydrogen/deuterium isotope effect, we propose a new technique to separate and quantify the effects of hot-carrier-induced interface trap creation and oxide charge trapping on the degradation in PMOSFETs. In addition to the well-known hot-electron-induced-punchthrough (HEIP) mechanism, we find that two additional mechanisms, namely, interface trap creation and hole trapping in the oxide, also play important roles in PMOSFET degradation. The degradation mechanisms are highly dependent on stress conditions. For low gate voltage V_gs stress, HEIP is found to dominate the shift of threshold voltage V_t. When V_gs increases to a moderate value, the V_t shift can be fully dominated by interface trap creation. Hole injection and trapping into the oxide occurs when V_gs is increased further to V_gs=V_ds. For the first time, the effects of interface trap creation and oxide charge trapping on the V_t shift are quantified by the proposed technique     

In-depth exploration of Si-SiO2 interface traps in MOStransistors using the charge pumping technique

It is shown that the charge pumping (CP) technique can be used for extraction of the depth concentration profile of traps situated in the oxide of metal-oxide-semiconductor (MOS) transistors, near and at the Si-SiO₂ interface. The trap density is obtained from the variation of the charge pumping current as a function of frequency, the other measurement parameters being kept constant. The concentration profiles are measured on n and p-channel transistors from several technologies, and on virgin and stressed devices. The results show that the trap concentration decreases rapidly from the Si-SiO₂ interface in the direction of the oxide depth and suggest that it becomes constant at a fraction of a nanometer from the silicon interface. The method easily demonstrates the trap creation due to Fowler-Nordheim stress. The profiles compare favorably with those measured using a new drain-current transient technique. In all cases, the integration of the depth concentration profiles leads to the interface trap densities measured using the conventional charge pumping method     

Characterization of oxide trap and interface trap creation duringhot-carrier stressing of n-MOS transistors using the floating-gatetechnique

A technique has been developed to differentiate between interface states and oxide trapped charges in conventional n-channel MOS transistors. The gate current is measured before and after stress damage using the floating-gate technique. It is shown that the change in the I_g-V_g characteristics following the creation and filling of oxide traps by low gate voltage stress shows distinct differences when compared to that which occurs for interface trap creation at mid gate voltage stress conditions, permitting the identification of hot-carrier damage through the I_g- V_g characteristics. The difference is explained in terms of the changes in occupancy of the created interface traps as a function of gate voltage during the I_g-V _g measurements     

Observation of single interface traps in submicron MOSFET's bycharge pumping

The observation of single interface traps in small area MOSFET's by charge pumping is demonstrated for the first time, The dependence of the single trap charge pumping current on the base level voltage is described, Also the creation of one single interface trap under influence of low level hot carrier injection is demonstrated. A prediction of the charge pumping current behavior as a function of rise and fall time and temperature for the case of individual traps is made. The correlation with RTS-noise experiments is discussed     

Spatial Distributions of Trapping Centers in HfO2/SiO2 Gate Stack

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO ₂/HfO₂ gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO₂ layer and HfO₂/SiO₂ interface region. The trap density in the SiO₂ layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO₂ layer     

A lifetime prediction method for oxide electron trap damage createdduring hot-electron stressing of n-MOS transistors

Electron trap creation under conditions of hot-electron stress (i.e., stress at V_d=V_g) is examined. It is shown that a relationship exists linking lifetime to the injected gate current and drain current, offering a lifetime prediction method for these types of traps. Comparing this type of damage to interface trap (N_it) creation, it is found that larger energies (approximately 1.5 times that for N_it) are required to generate this defect. It is shown that an extrapolation technique can be used to obtain gate currents at working circuit voltages, extending the prediction of lifetimes for oxide trap creation to low voltages     

On the SILC mechanism in MOSFET’s with ultrathin oxides

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I_g(V_g), characteristics is thought to flow through Si–SiO₂ interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO₂ interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.     

On the time-dependent degradation of LDD n-MOSFETs under hot-carrier stress

A unified model for hot-carrier-induced degradation in LDD n-MOSFETs is presented. A novel oxide spacer charge pumping method enables interface trap generation in the spacer and overlap/channel regions to be distinctly separated. An excellent correlation between trap generation in the spacer region and linear drain current degradation at high gate voltage is observed. Moreover, trap generation in the overlap/channel region is found to correlate well with linear drain current degradation at low gate voltage. The results point unambiguously to a two-mechanism degradation model involving drain resistance increase by trap generation in the spacer region, and carrier mobility reduction by trap generation in the overlap/channel region. The combined effect of a time-independent lateral electron temperature profile and a finite density of interface trap precursors within the LDD region leads to a self-limiting degradation behavior. This insight forms the basis of a time-dependent trap generation model, which indicates the existence of a single degradation curve. The fact that the degradation curves at different stress drain voltages fall onto a time-scaled version of the single degradation curve provides strong support for the model. This also offers a straightforward and yet accurate means by which the hot-carrier lifetime corresponding to a specific failure criterion may be extracted. Finally, a power-law relationship between hot-carrier lifetime and substrate current is also observed for the LDD devices, thus preserving the physical essence based on which earlier lifetime models for conventional drain devices are established.     

Studies of the quality of GdSiO-Si interface

In this paper nMOS transistors with GdSiO gate dielectric are studied using electrical methods (C-V, I-V and charge pumping) in order to assess the quality of the dielectric-semiconductor interface. Mobility is estimated using the split C-V technique and the influence of voltage stress on interface trap generation and charge build-up in the oxide is investigated. Generation of additional interface traps is observed during negative voltage stress only, which may be attributed to hole tunneling from the semiconductor to electron traps. Multi-frequency charge pumping measurements reveal the presence of border traps.