Sensitivity measurement of a 10.6-µm parametric upconverter

The sensitivity of a parametric upconverter for the detection of 10.6-µm radiation was measured. 10.6-µm radiation was mixed with the 1.06 µm beam of an Nd :YAG laser in properly oriented single-crystal proustite. The upconverted output at 0.967 µm was then detected by an S-1 photomultiplier tube. NEP of 1.1×10^-9W . s^½was measured.     

Computer-controlled scanning electron microscope system for high-resolution microelectronic pattern fabrication

A small, dedicated computer has been interfaced to a scanning electron microscope (SEM) for the purpose of generating, registering, and fabricating microelectronic device and circuit patterns with submicron dimensions. A preliminary registration accuracy of ±0.1 µm over a (950-µm)²pattern field has been demonstrated.     

AlGaAs/GaAs heterojunction bipolar transistors fabricated using a self-aligned dual-lift-off process

This paper describes a self-aligned heterojunction-bipolar-transistor (HBT) process based on a simple dual-lift-off method. Transistors with emitter width down to 1.2 µm and base doping up to 1 × 10²⁰/cm³have been fabricated. Extrapolated current gain cutoff frequency ftof 55 GHz and maximum frequency of oscillationf_{max}of 105 GHz have been obtained. Current-mode-logic (CML) ring oscillators with propagation delays as low as 14.2 ps have been demonstrated. These are record performance results for bipolar transistors. The dual-lift-off process is promising for both millimeter-wave devices and large-scale integrated circuit fabrication.     

A 1-µm bipolar VLSI technology

A 1-µm VLSI process technology has been developed for the fabrication of bipolar circuits. The process employs electron-beam slicing writing, plasma processing, ion implantation, and low-temperature oxidation/annealing to fabricate bipolar device structures with a minimum feature size of 0.9 µm. Both nonisolated I²L and isolated Schottky transistor logic (STL) devices and circuits have been fabricated with this process technology. The primary demonstration vehicle is a scaled LSI, I²L, 4-bit processor chip (SBP0400) with a minimum feature size of 1 µm. Scaled SPB0400's have been fabricated that operate at clock speeds 3 × higher than their full-size counterparts at 50-mA chip current. Average propagation delay has been measured as a function of minimum feature size for both I²L and STL device designs. Power-delay products of 14 fJ for I²L and 30 fJ for STL have been measured.     

Large-area and visible response VPE InGaAs photodiodes

InGaAs photodiodes having diameters of 500 µm have been successfully fabricated by vapor-phase epitaxial techniques. Typical room-temperature performance characteristics at a bias voltage of -10 V are: quantum efficiency ≈80 percent (1 to 1.7 µm); dark current &ap120 nA; noise current &ap0.3 pA/Hz^1/2; capacitance &ap5 pF; and response time &ap3 ns. The useful spectral range of standard 100-µm-diameter diodes has been extended to short Wavelengths (about 0.5 µm) by a reduction in the thickness of the InP capping layer. Quantum efficiencies near 70 percent have been observed at 0.7 µm.     

InGaAsP/InP 1.3-µm wavelength surface-emitting LED's for high-speed short-haul optical communication systems

Performance and reliability for InGaAsP/InP 1.3-µm wavelength high-speed surface-emitting DH light emitting diodes (LED's) have been investigated. High-speed and high-radiance performances were obtained by the optimal design of both structural parameters and LED driving circuit. Rise and fall times were both 350 ps and peak optical power coupled to a 50-µm core 0.20 NA graded-index fiber at the 100-mA pulse current was - 15.8 dBm with 6-dB optical ON/OFF ratio. A 2-Gbit/s non-return-to-zero (NRZ) pulse transmission over a 500-m span was carried out, Feasibility of using surface-emitting LED's in a high-speed optical communication system has been confirmed. Accelerated aging tests on high-speed LED's were carried out. The half-power lifetimes have been estimated to be more than 1 × 10⁸h at 50°C ambient temperature.     

Efficient 1.06-µm emission from InxGa1-xAs electroluminescent diodes

Vapor-grown p-n junctions of InxGa1-xAs have been prepared that emit near-bandgap infrared radiation at 1.06 µm with an external quantum efficiency in excess of 1 percent at room temperature. These diodes have an electroluminescence response time of 20 ns. In addition, InxGa1-xAs injection lasers have been fabricated with threshold current densities between 2000 and 3000 A/cm²at 80 K. The importance of internal absorption losses in determining the spectral distribution and the electroluminescence efficiency at room temperature is described.     

CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques

A CMOS analogue current-mode multiplier/divider circuit is presented. It is based on a dynamic biasing applied at the bulk terminal of MOS transistors operating in both saturation and triode. With the proposed structure, the multiplier forms a feedback loop that improves the current swing and accuracy. The multiplier has been fabricated using a standard 0.18 µm CMOS technology. The circuit consumes 144 µW using a single supply voltage of 1.8 V with a measured THD lower than 1% for an output current of 38 µA, and requires a die area of 90 µm x 45 µm.     

Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

Impurity distribution in high-efficiency silicon avalanche diode oscillators

The influence of impurity distribution on the performance of high-efficiency silicon avalanche diode oscillators has been investigated for a number of diffusion profiles and doping densities of ionized donors. p⁺-n-n⁺mesa diodes with diameters ranging from 0.005 to 0.030 inch, were designed with abrupt, hyperabrupt, graded, and linearly graded junctions with doping densities varying from 10¹⁴to 2 × 10¹⁵cm^-3and depletion region width 4 µm ≤ W ≤ 8 µm. The devices were operated at L-band with 40 percent efficiency. The high-frequency characteristics of the avalanche devices have shown that high-efficiency performance can be achieved with complex waveforms of current.     

Optimization of GaAs power MESFET device and material parameters for 15-GHz operation

The results of recent 15-GHz measurements on GaAs power FET's are described. The microwave performance has been determined as a function of epitaxial doping level and thickness, gate recess depth, gate finger width, and source-drain spacing. The optimum values of these parameters for 15-GHz operation are epitaxial doping level approximately 1.6 × 10¹⁷cm^-3, saturated drain current with zero gate voltage in the range 330- to 400-mA/mm gatewidth, gate recess depth between 500 and 1000 Å, gate finger width ≤ 150 µm, and source-drain spacing approximately 5 µm.     

A 4K-bit static I2L memory

A 4096-bit ECL random-access memory using high-density I²L memory cell has been developed. Novel ECL circuit techniques and I²L flip-flop memory cells are introduced for realizing high-speed performance, low-power operation, and small chip size. It operates typically under 20-ns access time and 300 mW of power dissipation, realizing 1.46 pJ/bit of access time and power-per-bit product, a figure of merit of memory devices. The memory cell and chip size of 1122 µm²(33 µm × 34 µm) and 9.9 mm²(3 mm × 3.3 mm), respectively, are achieved with V-groove isolated bipolar process technology. The memory is organized into 4096 words × 1 bit, and is packaged into 18-pin DIP and also 18-pad leadless chip carrier package. Development results have shown that the n-p-n-coupled superintegrated I²L flip-flop memory cell is very promising for high-speed and low-power static RAM's above 4K-bit/chip area.     

Limitations on injection efficiency in power devices

In this paper the mechanisms of bandgap narrowing, Shockley-Read-Hall (SRH) recombination, Auger recombination, and carrier-carrier and carrier-lattice scattering are included in an exact one-dimensional model of a bipolar transistor. The transistor is used as a vehicle for studying the relative importance of each of these phenomena in determining emitter efficiency in devices with emitter junction depths of 1 µm to 8 µm. It is shown that bandgap narrowing is the dominant influence for devices with shallow emitters of 2 µm or less and that SRH recombination dominates for emitter depths greater than 4 µm. Calculations are also presented showing the effects of the emitter surface concentration and high-level injection on the current gain for devices with emitter junction depths of 1 µm to 8 µm. It is shown that there is an optimum surface concentration of 5 × 10¹⁹cm^-3for the 1-µm emitter depth but no optimum under 10²¹cm^-3for devices with emitter depths greater than 4 µm.     

RECIPE—A two-dimensional VLSI process modeling program

REnsselaer Computer integrated Circuits Process Engineering (RECIPE) is a two-dimensional (2-D) integrated circuit process modeling program developed for use in VLSI applications. The program incorporates a 2-D diffusion model which includes the concentration dependence of the diffusion coefficients. An incremental solution method is used to compute the appropriate diffusion coefficients as a function of impurity concentration throughout space. RECIPE also incorporates a 2-D ion-implantation model. While intended as a general-purpose modeling program, RECIPE has been used to study channel-length decrease of short-channel MOSFET's during high-temperature processing. A typical phosphorus-implanted (150 keV, 10¹⁶/cm²) 1-µm gate transistor had no channel after processing for 60 min at 1000°C, while an arsenic-implanted device had an effective channel length of ∼ 0.1 µm after similar processing.     

A high-current drivability i-AlGaAs/n-GaAs doped-channel MIS-Like FET (DMT)

A high-current drivability doped-channel MIS-like FET (DMT) has been proposed. The DMT takes advantage of high saturation current with large transconductance and high breakdown voltage, in regard to its operating principle. The fabricated 0.5-µm gate DMT showed 310-mS/mm (410-mS/mm) transconductance and 650-mA/mm (800-mA/mm) maximum saturation current at room temperature (at 77 K). Output current values are about three or four times those for conventional two-dimensional electron gas (2DEG) FET's. Estimated average electron velocity is rather high, 1.5 × 10⁷cm/s (2 × 10⁷cm/s) at room temperature (77 K). In addition,f_{max}is as high as 41 GHz. fTis 45 GHz, which is the best data ever reported in 0.5-µm gate FET's.     

A dc and microwave comparison of GaAs MESFET's on GaAs and Si substrates

In order to assess GaAs on Si technology, we have made a performance comparison of GaAs MESFET's grown and fabricated on Si and GaAs substrates under identical conditions and report the first microwave results. The GaAs MESFET's on Si with 1.2-µm gate length (290-µm width) exhibited transconductances (gm) of 180 mS/mm with good saturation and pinchoff whereas their counterparts on GaAs substrates exhibited gmof 170 mS/mm. A current gain cut-off frequency of 13.5 GHz was obtained, which compares with 12.9 GHz observed in similar-geometry GaAs MESFET's on GaAs substrates. The other circuit parameters determined from S-parameter measurements up to 18 GHz showed that whether the substrate is Si or GaAs does not seem to make a difference. Additionally, the microwave performance of these devices was about the same as that obtained in devices with identical geometry fabricated at Tektronix on GaAs substrates. The side-gating effect has also been measured in both types of devices with less than 10-percent decrease in drain current when 5 V is applied to a pad situated 5 µm away from the source. The magnitude of the sidegating effect was identical to within experimental determination for all side-gate biases in the studied range of 0 to -5 V. The light sensitivity of this effect was also very small with a change in drain current of less that 1 percent between dark and light conditions for a side gate bias of -5 V and a spacing of 5 µm. Carrier saturation velocity depth profiles showed that for both MESFET's on GaAs and Si substrates, the velocity was constant at 1.5 × 10⁷cm/s to within 100-150 Å of the active layer-buffer layer interface.     

Mo- and Ti-silicided low-resistance shallow junctions formed using the ion implantation through metal technique

Mo-and Ti-silicided junctions were formed using the ITM technique, which consists of ion implantation through metal (ITM) to induce metal-Si interface mixing and subsequent thermal annealing. Double ion implantation, using nondopant ions (Si or Ar) implantation for the metal-Si interface mixing and dopant ion (As or B) implantation for doping, has resulted in ultrashallow ( ≤ 0.1-µm) p⁺-n or n⁺-p junctions with ∼30-Ω sheet resistance for Mo-silicided junctions and ∼5.5-Ω sheet resistance for Ti-silicided junctions. The leakage current levels for the Mo-silicided n⁺-p junctions (0.1-µm junction depth) and the Mo-silicided p⁺-n junction (0.16-µm junction depth) are comparable to that for unsilicided n⁺-p junction with greater junction depth ( ∼0.25 µm).     

A low-voltage high-speed silicon photodiode with buried isolation region for short-haul optical-fiber communications

A new epitaxial silicon p-i-n photodiode has been developed for short-haul optical-fiber communications that can be operated at biases as low as 4 V. The device has a heavily doped 5-µm-thick p⁺⁺isolation-region between the p⁺substrate and the π-epitaxial layer. Fast rise and fall times (2 ns), and low leakage current (40 pA) result from the recombination and trapping of the minority-carrier electrons in the substrate. Experimental results on such an n⁺-π-p⁺⁺-p⁺device with 1.1-mm²photosensitive area and 25-µm epi-layer thickness show quantum efficiency of 80 percent at 825-nm wavelength.     

Ga0.4In0.6As/Al0.55In0.45As pseudomorphic modulation-doped field-effect transistors

High-performance pseudomorphic Ga0.4In0.6As/ Al0.55In0.45As modulation-doped field-effect transistors (MODFET's) grown by MBE on InP have been fabricated and characterized. DC transconductances as high as 271, 227, and 197 mS/mm were obtained at 300K for 1.6-µm and 2.9-µm gate-length enhancement-mode and 2-µm depletion-mode devices, respectively. An average electron velocity as high as 2.36 × 10⁷cm/s has been inferred for the 1.6-µm devices, which is higher than previously reported values for 1-µm gate-length Ga0.47In0.53As/Al0.48In0.52As MODFET's. The higher bandgap Al0.55In0.45As pseudomorphic barrier also offers the advantages of a larger conduction-band discontinuity and a higher Schottky barrier height.     

A comparison of Nd:YAG fundamental and second-harmonic Q-switched laser-beam lifetime doping in single-crystal silicon

Silicon devices including bipolar transistors, junction diodes, and MOS capacitors were scanned by aQ-switched Nd:YAG (1.06 µm) and frequency-doubled Nd:YAG (0.53 µm) radiations under various conditions. The electrical characteristics of these devices were measured before and after scanning and again after thermal annealing. The data includes transistor gain versus laser power; junction diode leakage current versus junction depth; MOSC-Vlifetime versus laser power and the effects of subsequent thermal anneals on all of these. The results are that bulk minority-carrier lifetime decreases of several orders of magnitude will be produced by either of these radiations at peak power levels below those which will produce any visible surface damage. The changes in minority-carrier lifetime are stable for post scanning thermal anneals up to 400°C and are almost completely removed from an 800°C anneal. The depths within which minority-carrier lifetime changes significantly are 0.7 and 1.8 µm for 0.53- and 1.06-µm wavelength laser radiations, respectively. The results indicate that the recombination centers produced by the scanning are point defects and their density decreases exponentially with the distance into the silicon. The average power thresholds for point defect production (for both 0.53- and 1.06-µm wavelengths) were determined and are observed to increase with increased laser wavelength and pulse width. Potential applications in silicon devices and integrated circuits such as selective lifetime doping, β trimming, and selective-link making without passivation damage are possible.