A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

A 1-μm polysilicon self-aligning bipolar process for low-powerhigh-speed integrated circuits

A double-poly-Si self-aligning bipolar process employing 1-μm lithography is developed for very-high-speed circuit applications. Epilayer doping and thickness are optimized for breakdown voltages and good speed-power performance. Shallow base-emitter profiles are obtained by combining low-energy boron implantation and rapid thermal annealing (RTA) for the emitter drive-in. A transit frequency f_T =14 GHz at V_BC=-1 V and a current-mode-logic (CML) gate delay of 43 ps at 30 fJ are achieved. For an emitter size of 1.0×2.0 μm² a minimum power-delay product of 15 fJ is calculated. Circuit performance capability is demonstrated by a static frequency divider operating up to 15 GHz     

A new parameter extraction technique for small-signal equivalentcircuit of polysilicon emitter bipolar transistors

We propose a new parameter extraction method for advanced polysilicon emitter bipolar transistors. This method is based on the predetermination of equivalent circuit parameters using the analytical expressions of de-embedded Z-parameters of these devices. These parameter values are used as initial values for the parameter extraction process using optimization. The entire device equivalent circuit, containing RF probe pad and interconnection circuit parameters extracted by test structures, is optimized to fit measured S-parameters for eliminating de-embedding errors due to the imperfection of pad and interconnection test structures. The equivalent circuit determined by this method shows excellent agreement with the measured S-parameters from 0.1 to 26.5 GHz     

A new polysilicon CMOS self-aligned double-gate TFT technology

In this paper, a new polysilicon CMOS self-aligned double-gate thin-film transistor (SA-DG TFT) technology is proposed and experimentally demonstrated. The self-alignment between the top- and bottom-gate is realized by a backlight exposure technique. The structure has an ultrathin channel region (300 /spl Aring/) and a thick source/drain region. Experimental results show that this technology provides excellent current saturation due to a combination of the effective reduction in the drain field and the full depletion of the ultrathin channel. Moreover, for n-channel devices, the SA-DG TFT has a 4.2 times higher on-current (V/sub gs/=20V) as compared to the conventional single-gate TFT. Whereas for the p-channel devices, the SADG TFT has a 3.6 times higher on-current (V/sub gs/=-20V) compared to the conventional single-gate device.     

A polysilicon contacted subcollector BJT for a three-dimensionalBiCMOS process

A polysilicon contacted subcollector (PCS) bipolar junction transistor (BJT) was fabricated using selective epitaxial growth (SEG) of silicon to form the active region. The fabrication is the first step in the development of a novel 3-D BiCMOS process. To study the efficacy of the polysilicon collector contact, three types of BJTs were fabricated and their collector resistances were compared. These were the PCS BJT, a BJT fabricated in SEG silicon grown from a shallow trench incorporating a shallow collector contact with a buried layer, and a BJT fabricated in the silicon substrate with a shallow collector contact but no buried layer. The PCS BJT exhibited the smallest collector resistance as well as excellent device characteristics, demonstrating its viability for a 3-D BiCMOS process     

In situ phosphorus-doped polysilicon emitter technology for veryhigh-speed, small emitter bipolar transistors

In situ phosphorus-doped polysilicon emitter (IDP) technology for very high-speed, small-emitter bipolar transistors is studied. The device characteristics of IDP transistors are evaluated and compared with those of conventional ion-implanted polysilicon emitter transistors. IDP technology is used to fabricate double polysilicon self-aligned bipolar transistors and the I-V characteristics, current gain, transconductance, emitter resistance, and cut-off frequency are measured. In conventional transistors, these device characteristics degrade when the emitter is small because of the emitter-peripheral-thick-polysilicon effect. In IDP transistors, the peripheral effect is completely suppressed and large-grain, high-mobility polysilicon can be used. The device characteristics, therefore, are not degraded in sub-0.2-μm emitter transistors. In addition, large-grain, high-mobility, and high phosphorus concentration IDP films increase current gain and lower emitter resistance. The use of IDP technology to build very small emitter transistors is evaluated and discussed     

Physics, technology, and modeling of polysilicon emitter contacts for VLSI bipolar transistors

The physics of minority-carrier injection into polysilicon-contacted emitters has been studied through a series of experiments correlating the base current of the transistor to the structure of the polysilicon/single-crystal silicon interface. Most of the relevant material and processing parameters have been examined. In addition, a novel approach has been taken in the modeling of transport in these emitters to quantify the minority-carrier blocking properties of the polysilicon contacts. Experimental results show that extremely low values of base current can be obtained for devices etched in HF prior to the polysilicon deposition, i.e., devices with only a remnant "native" oxide layer at the polysilicon/single-crystal silicon interface. For these devices, the base current is mainly determined by the recombination and blocking of minority carriers at the polysilicon/monosilicon interface. A number of competing mechanisms exist in several domains of doping, temperature, and time which influence the properties of this interface. One of these mechanisms is the blocking of minority carriers by the native oxide layer itself. The uniformity and, consequently, the blocking characteristics of this layer were found to be strongly affected by the polysilicon doping level and thermal treatment.     

Self-aligned transistors with polysilicon emitters for bipolar VLSI

A new bipolar process technology for fabricating self-aligned transistors with polysilicon contacted emitters is described. The extrinsic base regions of the transistor are self-aligned to the emitter contact by exploiting the effects of concentration-dependent oxidation to selectively oxidize the polysilicon. The shallow emitter is fabricated with a thin oxide layer at the polysilicon-silicon interface, thereby enhancing the emitter efficiency and thus the current gain of the device. It is demonstrated that this gain enhancement can be traded for a considerable increase in active base doping, with a resulting decrease in base resistance and potential improvement in switching performance. Under certain circumstances, non-ideal electrical characteristics can be obtained from the self-aligned transistor which are caused by lateral spread of the extrinsic base region beneath the sidewall oxide of the polysilicon emitter contact. This leads to the formation of p⁺-n⁺junction at the periphery of the emitter and hence to tunneling of carriers across this region. It is shown that the same tunneling mechanism also limits the extent to which the active base doping can be increased. In order to avoid the formation of the peripheral p⁺-n⁺junction, a polysilicon base contact is employed which allows a self-aligned extrinsic base region to be fabricated with negligible lateral movement.     

Vertical bipolar transistors in laser-recrystallized polysilicon

Vertical bipolar n-p-n transistors with a base width of 0.2 µm have been fabricated in laser-recrystallized polysilicon films on thermally oxidized silicon substrates. With proper hydrogen annealing steps, common-emitter current gains on the order of 100 were possible. Recombination in the base-emitter space-charge region was found to be the dominant source of base current.     

Low-temperature process for high-mobility polysilicon TFTs

Thin-film transistors (TFTs) have been realised by a low-temperature (T? 580°C), short process, on polycrystalline silicon thin films deposited by PECVD on glass. Field-effect mobility up to 35cm2V-1s-1 has been measured on such devices.     

Low-cost process for fabricating polysilicon transistors

A process for the fabrication of p-channel polysilicon MOS transistors is described. The process is compatible with the use of low-temperature glass substrates and replaces the use of ion implantation for the source/drain doping with in situ doped polysilicon. MOS transistors made with this process exhibit an on/off current ratio of 2.5×10⁵, a mobility of 16 cm²/V-s, and a subthreshold slope of 1.3 V/decade     

A vertical submicron polysilicon thin-film transistor using a lowtemperature process

This letter presents a submicron (0.5 μ) vertical N-channel MOS thin-film transistor (TFT) fabricated in Polycrystalline Si using a simple low temperature process (⩽600°C). The channel length is determined by the thickness of an SiO₂ film. As a result, submicron vertical polysilicon TFT's can be fabricated without submicron lithographic equipment that is not yet available for large area active matrix liquid crystal display (AMLCD) applications. The device has a dynamic range of greater than five orders of magnitude after hydrogenation     

Statistical simulation of IC technology: A bipolar process example

Statistical simulation using design of experiments has been employed for integrated circuit technology development. A software program called STADIUM was developed to implement this statistical methodology. The software has been designed to be user friendly and to guide the engineer who is not a statistics expert through the process of deriving a valid statistical answer. Inputs to the STADIUM system include integrated circuit fabrication variations and when coupled with semiconductor process and device simulators can estimate the expected variations of device parameters such as transistor gain and threshold voltage. This paper presents the detailed procedure and results of a statistical simulation of a bipolar transistor technology.     

Effective recombination velocity of polysilicon contacts for bipolar transistors

The effective surface recombination velocity is determined analytically for a doped polysilicon contact to the emitter of a bipolar transistor in the presence of a thin interfacial oxide layer. Results are presented for various doping levels, oxide thicknesses and barrier heights. The analysis considers both tunnelling and thermionic emission through the interface.     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

A nonrecessed-base, self-aligned bipolar structure with selectivelydeposited polysilicon emitter

A self-aligned bipolar structure, which features a nonrecessed base and a selectively deposited polysilicon emitter, is proposed. The in situ surface cleaning process prior to the selective-polysilicon deposition minimizes the residual native oxide in the emitter window. Both high-quality selective-polysilicon film and well-behaved submicrometer bipolar device characteristics have been obtained for bipolar or BiCMOS VLSI applications. The effects of the nonrecessed-base device structure on the bipolar device parameter distribution and bipolar hot-carrier immunity are also discussed     

A new method for realizing JFETs and super B's in a standard bipolar IC process

A new method for the realization of p-channel JFETs is presented. It is based on the removal of thin silicon layers by repeated anodic oxidation and etching, allowing the shallow-n (SN) diffusion to penetrate deeper into the shallow-p (SP) region. JFETs with a thin channel are thus obtained with a high yield and good reproducibility.     

A new laser-processed polysilicon TFT architecture

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm²/Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents     

Low-frequency noise in polysilicon emitter bipolar transistors

The low-frequency noise in polysilicon emitter bipolar transistors is investigated. Transistors with various geometries and various properties of the oxide layer at the monosilicon polysilicon interface are studied. The main 1/f noise source proved to be located in the oxide layer. This source causes both 1/f noise in the base current S_Ib and 1/f noise in the emitter series resistance S_re The magnitude of the 1/f noise source depends on the properties of the oxide layer. The 1/f noise is ascribed to barrier height fluctuations of the oxide layer resulting in transparency fluctuations for both minority and majority carriers in the emitter, giving rise to S_Ib and S _re respectively. It is also shown that a low transparency of the oxide layer also reduces the contribution of mobility fluctuations to S_Ib     

A 30-ps Si bipolar IC using super self-aligned process technology

A new 30-ps Si bipolar IC technology has been developed by scaling down a bipolar transistor's lateral geometry and forming shallow junctions. The n-p-n transistor has a 0.35-µm-wide emitter and a 1.57-µm-wide base region fabricated using super self-aligned process technology (SST) with 1-µm rule optical lithography. The fTvalues achieved for this device are 13.7 GHz at a collector-emitter voltage of 1 V and 17.1 GHz at 3 V. Propagation delay times (fan-in = fan-out = 1) of 30 ps/gate at 1.48 mW/gate for nonthreshold logic and 50 ps/ gate at 1.46 mW/gate for low-level current mode logic have been achieved.