共查询到18条相似文献,搜索用时 78 毫秒
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文章提出了基于全1多项式基的可伸缩分组并行有限域乘法器结构,并按照最低位先入和最高位先入的方式分别进行了算法描述,分别称为AOPBLSDM(AOP-Based LSD-first Digital-Serial Multiplier)和AOPBMSDM(AOP-Based MSD-first Digital-Serial Multiplier)。该乘法器的结构规整,适于VLSI实现;同时由于该乘法器具有面积和速度可伸缩度大的特点,因而可以在不同的应用场合下找到最佳的实现方案。理论分析及ASIC综合实现结果均表明,本文所提出的结构在面积和速度上具有一定的优势。 相似文献
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本文首先分析了一类GF(2~n)上的算术运算,然后讨论了在这类GF(2~n)上实现椭圆曲线密码体制的方法,最后列出了我们在GF(2~(178))上实现的椭圆曲线密码体制的结果。 相似文献
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本文介绍了一种基于多项式基的有限域乘法的算法原理,此算法适用于任何本原多项式,因此是通用的.并在此基础上提出了一种新的有限域乘法器电路架构,其结构规正,易于扩展,适合工程实现,尤其适用于差错控制码领域的应用.设计结果表明,本实现方法在速度和面积上都优于传统的基于多项式基的LSB递归算法. 相似文献
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In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations. 相似文献
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提出了一种可配置的支持红外自动目标识别应用中不同窗口操作的2D空域滤波类操作VLSI架构,从SoC角度考虑能够更好地满足不同的图像处理应用.该架构与已报道的对于该类操作的其他结构解决方案进行比较,新结构具有较高的处理速率.新结构在SIMC0.18μmCMOS工艺下实现,其时钟频率为135Mhz,功耗为52mW,面积约为128.2KGates,峰值处理性能达到6.6GOPs. 相似文献
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详细介绍了在设计RS(256,252)译码器过程中所用的乘法器和除法器,两种器件具有规则的结构,有利于用VLSI硬件电路来实现。 相似文献
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可配置GF(2m)域Digit-Serial乘法器 总被引:1,自引:0,他引:1
本文针对椭圆加密算法的应用,基于已有的GF(2^m)域Digit—Serial不可配置乘法器,通过控制输入数据格式、内镶GF(2^m)域Digit—Serial不可配置乘法器,得到了一个在硬件上可配置的快速乘法器。运用本文的思想实现了可计算域值为150~256的GF(2^m)域Digit-Serial的乘法器,用此乘法器计算域值为163的乘法,仿真结果同域值为163的不可配置并行乘法器的一致。本文最后还给出了几种可配置乘法器结构的性能比较,结果表明在硬件上可配置的GF(2^m)域乘法器解决方案中,本文提出的结构克服了并行可配置乘法器在大域值应用中关键路径延迟太长、硬件开销太大,串行可配置乘法器实现速度太慢的弊病。需要说明的是,本文的实现方法可以内镶各种不同的GF(2^m)域Digit-Serial不可配置乘法器以满足实际应用的需要。 相似文献
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In this paper we present a low complexity discrete cosine transform (DCT) architecture based on computation re-use in vector-scalar
product. 1-D DCT operation is expressed as additions of vector-scalar products and basic common computations are identified
and shared to reduce computational complexity in 1-D DCT operation. Compared to general distributed arithmetic based DCT architecture,
the proposed DCT shows 38% of area and 18% of power savings with little performance degradation. We also propose an efficient
method to trade off image quality for computational complexity. The approach is based on the modification of DCT bases in
bit-wise manner and different computational complexity/image quality trade-off levels are suggested. Finally, based on the
above approaches, we propose a low complexity DCT architecture, which can dynamically reconfigure from one trade-off level
to another. The reconfigurable DCT architecture can achieve power savings ranging from 28% to 56% for 3 different trade-off
levels.
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Kaushik RoyEmail: |
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针对目前缩1码模2n+1乘法器的优缺点,设计出一个有效的缩1码模2n+1乘法器。该模乘法器是由改进的基-4 Booth编码模块、规整的缩1码进位保留加法器树以及缩1码模加法器构成,部分积的个数减少到n/2+2个,具有统一的编码电路,简单的校正项生成电路,较快的计算速度,尤其是能够处理操作数和结果为0的情况,实现了操作数的全输入。比较结果表明,该模乘法器在同类型模乘法器中以最少的面积获得了更快的速度。 相似文献