一种新型快速有限域乘法器设计实现

介绍一种新型有限域乘法器,其基本原理是引入多项式拆分概念和多项式拆分方法,将m次的多项式拆分成两个m/2次多项式分别做有限域乘法,这样可以降低乘法运算的阶数,用加法计算电路来代替。并且根据这种算法设计了新型乘法器的电路实现,将这种新型乘法器并且与比特串行乘法器的仿真结果做对比。结果表明新型的有限域乘法器达到了较高的系统数据吞吐率,可以应用于纠错系统、RS编码器和译码器中。     

一种快速有限域乘法器结构及其VLSI实现

提出了一种快速有限域乘法器结构.将多项式被乘数与乘数各自平分成两个子多项式,并使用数字乘法结构计算这些子多项式的乘积.通过改变数字乘法结构的数字大小D,来均衡乘法器性能和实现复杂度.为了简化模不可约多项式f(x)运算,采用特殊多项式AOP(all one polynomials)和三项式,产生有限域GF(2m).这种乘法器与LSD乘法器相比,在数字大小D相同时,可将运算速度提高1倍.这种乘法器结构适合高安全度密码算法的VLSI设计.     

一种低复杂度RS编码器的FPGA实现

提出了一种新的基于标准基的有限域并行常系数乘法器结构,使用该结构设计了低复杂度的RS(204,188)编码器.该编码器由15个常系数乘法器构成.每个常系数乘法器通过共享一些相同硬件操作,使得编码器中异或门XOR的数目减少了30%左右.最后在FPGA上实现了该编码电路,并用QuartusⅡ7.2自带的SignalTap逻...     

基于脉动阵列结构的多项式基乘法器的设计

提出了一类基于脉动阵列结构的字串行有限域乘法器架构。架构基于多项式基,支持m相似文献   

高速Berlekamp-Massey算法结构及电路实现

介绍了两种用于二进制BCH解码器的高速Berlekamp—Massey算法实现方案。在加入寄存器以减少关键路径的延时从而提高电路速度的基础上，一种方法是采用有限域乘法器复用的方法降低电路的复杂度；另一种方法则通过对有限域乘法器进行流水线设计，进一步提高电路的工作速度，实现超高速应用。设计中充分利用了二进制BCH码中Berlekamp—Massey算法迭代计算时修正值间隔为零的性质，用超前计算的方法减少了运算周期的增加。提出的方案可用于设计高速光通信系统的信号编解码芯片。     

一种通用的有限域乘法器的设计与实现

本文介绍了一种基于多项式基的有限域乘法的算法原理,此算法适用于任何本原多项式,因此是通用的.并在此基础上提出了一种新的有限域乘法器电路架构,其结构规正,易于扩展,适合工程实现,尤其适用于差错控制码领域的应用.设计结果表明,本实现方法在速度和面积上都优于传统的基于多项式基的LSB递归算法.     

一种RS码译码器的硬件实现方法

提出了一种RS系统码译码器的硬件实现结构。译码器采用时域译码算法,主要包括有限域并行乘法器、BM迭代算法、适合于缩短码的钱氏搜索算法、错误值计算的硬件电路,其运算结构规则,具有一定的通用性,因此适合于VLSI实现。     

一种可重构的高速流水线乘法器

本文针对在语音、视频等信号处理中出现的变速率信号处理,提出了一种新型的高速高效可重构流水线乘法器电路,并在0.25μm工艺条件下对电路进行了仿真.该电路通过控制流水级数处理变速信号,可有效地节约电路资源约34%,同时可保证频率达1.8GHz的高运算速度.     

面向多媒体信息处理的可重构BOOTH乘法器设计

设计了一种新型可重构BOOTH乘法器.该乘法器在BOOTH编码、部分积生成、部分积压缩和最终加法器的设计中都充分考虑了可重构的需要,能方便快速地实现8位乘法器和16位乘法器之间的切换,便于在同一电路上实现基于字节和字的多媒体信息处理.该乘法器通过VHDL语言编程实现,采用XST综合,并通过Modelsim在XC2V4000上完成布局布线后仿真.试验结果表明:与基于乘法分配律的可重构乘法器相比,该方法具有占用资源少和速度快的优点.     

指纹识别专用集成电路中乘法器模块的设计

介绍了一种用于指纹识别专用集成电路(ASIC)的乘法器模块的设计.该乘法器模块能够处理32位的有符号数、无符号数的乘法和乘加运算.电路采用基-4的Booth编码以及改进型压缩器阵列结构.采用提出的迭代和阵列结合的结构算法,可节省芯片面积30%,提高工作频率24%.模块电路在TSMC 0.25 μm工艺上实现.该乘法器模块易于移植到其他数字处理系统.     

An efficient reconfigurable multiplier architecture for Galois field GF(2)

This paper describes an efficient architecture of a reconfigurable bit-serial polynomial basis multiplier for Galois field GF(2^m), where 1<m≤M. The value m, of the irreducible polynomial degree, can be changed and so, can be configured and programmed. The value of M determines the maximum size that the multiplier can support. The advantages of the proposed architecture are (i) the high order of flexibility, which allows an easy configuration for different field sizes, and (ii) the low hardware complexity, which results in small area. By using the gated clock technique, significant reduction of the total multiplier power consumption is achieved.     

New Multiplier for a Double‐Base Number System Linked to a Flash ADC

The double‐base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog‐to‐digital converters or digital systems through a double‐base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.     

High Performance Reconfigurable FIR Filter Architecture Using Optimized Multiplier

In mobile communication systems and multimedia applications, need for efficient reconfigurable digital finite impulse response (FIR) filters has been increasing tremendously because of the advantage of less area, low cost, low power and high speed of operation. This article presents a near optimum low- complexity, reconfigurable digital FIR filter architecture based on computation sharing multipliers (CSHM), constant shift method (CSM) and modified binary-based common sub-expression elimination (BCSE) method for different word-length filter coefficients. The CSHM identifies common computation steps and reuses them for different multiplications. The proposed reconfigurable FIR filter architecture reduces the adders cost and operates at high speed for low-complexity reconfigurable filtering applications such as channelization, channel equalization, matched filtering, pulse shaping, video convolution functions, signal preconditioning, and various other communication applications. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA) with a precision of 8-bits, 12-bits, and 16-bits filter coefficients. The proposed novel reconfigurable FIR filter architecture using dynamically reconfigurable multiplier block offers good area and speed improvement compared to existing reconfigurable FIR filter implementations.     

Customizable elliptic curve cryptosystems

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2/sup m/), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.     

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications

A run-time reconfigurable multiply-accumulate (MAC) architecture is introduced. It can be easily reconfigured to trade bitwidth for array size (thus maximizing the utilization of available hardware); process signed-magnitude, unsigned or 2's complement data; make use of part of its structure or adapt its structure based on the specified throughput requirements and the anticipated computational load. The proposed architecture consists of a reconfigurable multiplier, a reconfigurable adder, an accumulation unit, and two units for data representation conversion and incoming and outgoing data stream transfer. Reconfiguration can be done dynamically by using only a few control bits and the main component modules can operate independently from each other. Therefore, they can be enabled or disabled according to the required function each time. Comparison results in terms of performance, area and power consumption prove the superiority of the proposed reconfigurable module over existing realizations in a quantitative and qualitative manner.     

Design and implementation of a high-speed matrix multiplier based on word-width decomposition

This paper presents a flexible 2/spl times/2 matrix multiplier architecture. The architecture is based on word-width decomposition for flexible but high-speed operation. The elements in the matrices are successively decomposed so that a set of small multipliers and simple adders are used to generate partial results, which are combined to generate the final results. An energy reduction mechanism is incorporated in the architecture to minimize the power dissipation due to unnecessary switching of logic. Two types of decomposition schemes are discussed, which support 2's complement inputs, and its overall functionality is verified and designed with a field-programmable gate array (FPGA). The architecture can be easily extended to a reconfigurable matrix multiplier. We provide results on performance of the proposed architecture from FPGA post-synthesis results. We summarize design factors influencing the overall execution speed and complexity.     

Constant Number Serial Pipeline Multipliers

The pipeline form of the serial/parallel multiplier for constant numbers, which operates without insertion of zero words between successive data, is presented. The constant number is in Canonical Signed Digit (CSD) form and the other factor in two's complement form. The CSD form was chosen because it yields significant hardware reduction. Also, for the above data forms the Lyon's serial pipeline multiplier is examined. For these designs, a special algorithm for the multiplication of two's complement numbers with constant numbers in CSD representation was developed. The proposed serial pipeline multipliers are compared with the existing schemes from the point of hardware complexity.     

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

面向OFDM应用的低硬件开销低功耗64点FFT处理器设计

在基于正交频分复用(Orthogonal Frequency Division Multiplexing,OFDM)的无线系统中,快速傅里叶变换(Fast Fourier Transform,FFT)作为关键模块,消耗着大量的硬件资源。为此,针对于IEEE802. 11a标准的无线局域网基带技术,提出了一种低硬件开销、低功耗的基-24算法流水线架构FFT处理器设计方案。在硬件实现上,采用单路延迟负反馈(Single-path Delay Feedback,SDF)流水线架构;为了降低硬件资源消耗,基于新型的改良蝶形架构利用正则有符号数(Canonical Signed Digit,CSD)常数乘法器替代布斯乘法器完成所有的复数乘法运算。设计采用QUARTUS PRIME工具进行开发,搭配Cyclone 10 LP系列器件,编译结果显示该方案与其他已存在的方案相比,至少节约硬件成本25%,降低功耗18%。     

A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallelmultiplier

This paper presents a two's complement high-speed twin-pipe serial/parallel multiplier architecture which produces y=cd, where c is the parallel coefficient and d is the serial data. The multiplier is based on the twin pipeline (twin-pipe) concept, in which two data bits are processed each clock cycle. The high serial data throughput rate is mainly due to the use of: 1) a novel twin-pipe architecture, 2) new twin-pipe adder types, and 3) a new multiplier circuit structure. A 4-bit high-speed twin-pipe serial/parallel multiplier, on an active area of 0.224 mm², has been designed and fabricated in a 1.0-μm N-well double-metal single-poly CMOS process. Testing of the multiplier shows that the maximal serial data throughput rate is 965 Mb/s at V_dd=5 V