Hybrid cascode compensation with feedforward stage for high-speed area-efficient three-stage CMOS amplifiers

Hybrid cascode feedforward compensation (HCFC) is proposed for low-power area-efficient three stage amplifiers driving large capacitive loads. With no overhead in power or area, the total compensation capacitor is divided and shared between two internal high-speed loops instead of solely one loop as is common in prior art. Detailed analysis of HCFC shows significant improvement in terms of stability and bandwidth. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30 and 40 %, respectively, compared to the prevailing schemes.     

Dual-Miller Parallel Compensation for Low-Power Three-Stage Amplifier with a Wide Range of Capacitive Loads

In this paper, a dual-Miller parallel compensation (DMPC) technique for low-power three-stage amplifier is presented with detailed theoretical analysis. A feedback network realized by capacitor and transconductance is added between the first and third stage, which improves significantly the performance when driving large capacitive loads. Furthermore, it is found to be stable for a wide range of capacitive loads. The proposed DMPC amplifier has been implemented in a 0.13-μm CMOS process and the chip area is 0.17×0.11 mm². It achieves a 0.87 MHz gain-bandwidth product by consuming a total current of 41 μA. The DMPC amplifier is verified to be stable when the load capacitor ranges from 8 pF to 2 nF.     

Single Miller capacitor frequency compensation technique for low-power multistage amplifiers

Due to the rising demand for low-power portable battery-operated electronic devices, there is an increasing need for low-voltage low-power low-drop-out (LDO) regulators. This provides motivation for research on high-gain wide-bandwidth amplifiers driving large capacitive loads. These amplifiers serve as error amplifiers in low-voltage LDO regulators. Two low-power efficient three-stage amplifier topologies suitable for large capacitive load applications are introduced here: single Miller capacitor compensation (SMC) and single Miller capacitor feedforward compensation (SMFFC). Using a single Miller compensation capacitor in three-stage amplifiers can significantly reduce the total capacitor value, and therefore, the overall area of the amplifiers without influencing their stability. Pole-splitting and feedforward techniques are effectively combined to achieve better small-signal and large-signal performances. The 0.5-/spl mu/m CMOS amplifiers, SMC, and SMFFC driving a 25-k/spl Omega///120-pF load achieve 4.6-MHz and 9-MHz gain-bandwidth product, respectively, each dissipates less than 0.42 mW of power with a /spl plusmn/1-V power supply, and each occupies less than 0.02 mm/sup 2/ of silicon area.     

A Novel Frequency Compensation Technique for Three-Stage Amplifier

Multistage amplifiers are urgently needed with the advance in technology, due to the fact that single-stage cascode amplifier is no longer suitable in low-voltage designs. Moreover, the short-channel effects of the sub-micro CMOS transistor cause output-impedance degradation and hence the gain of an amplifier is reduced dramatically[1~6]. For multistage amplifiers, most of the compensation methods are based on pole splitting and pushing the right-half-plane zero to high frequencies or pole-ze…     

Analysis of multistage amplifiers with hybrid cascode feedforward compensation using a modified model for load impedance

Hybrid cascode feedforward compensation (HCFC) is an effective technique to stabilize nano-scale three-stage amplifiers driving ultra-large load capacitors. It divides the compensation capacitance and shares it between two high-speed local feedback loops embedded within the amplifier core. In this article, a systematic approach to analyze the transfer function and to evaluate the pole expressions of nano-scale HCFC amplifiers is presented. For the first time, the equivalent output impedance is successfully modeled to approximate the complicated transfer function of the HCFC amplifier without the need for lengthy pencil-and-paper calculations. An HCFC amplifier is designed and simulated in 90-nm CMOS technology, to verify the effectiveness of the new analytic approach. The simulated transfer function of the amplifier is almost identical to a calculated transfer function derived based on the new model.     

适合宽范围电容负载的三级运放

结合精确度和稳定性的要求提出了一种适合宽范围电容负载的CMOS运放.在多径嵌套式密勒补偿结构中加入一个抑制电容得到适合各种电容负载的稳定性.为了证实稳定性的提高对该结构进行了理论分析并计算得出数学表达式.基于这种新的频率补偿结构,利用CMOS 0.7μm工艺模型设计了样品芯片.测试结果表明:该运放可以驱动从100pF到100μF负载电容,直流增益为90dB,最小相位裕度为26°;该运放在100pF负载情况下单位增益带宽为1MHz,使用抑制电容仅为18pF.     

Single-Capacitor Active-Feedback Compensation for Small-Capacitive-Load Three-Stage Amplifiers

This brief presents a single-capacitor active-feedback compensation (SCAFC) scheme for three-stage internal amplifiers driving small capacitive loads. The proposed SCAFC scheme can stabilize the three-stage amplifier by using only a single small-value compensation capacitor, thereby significantly reducing the amplifier implementation area. With the small-value compensation capacitor, the wide gain-bandwidth product (GBW) of the SCAFC amplifier can also be achieved under low-power conditions. Implemented in a standard 0.35-mum CMOS process, the proposed three-stage SCAFC amplifier achieves over 100-dB dc gain, 9.6-MHz GBW, and 6.1-V/mus average slew rate, by only dissipating 90 muW at 1.5 V and using a 1-pF compensation capacitor, when driving a 500-kOmega // 20-pF load. The proposed SCAFC amplifier experimentally improves both bandwidth-to-power and slew-rate-to-power efficiencies by more than 14 times and 9 times, respectively, as compared to a conventional three-stage nested-Miller-compensated amplifier.     

AC-Boosting Frequency Compensation with Double Pole-Zero Cancellation for Multistage Amplifiers

In this paper, we present an AC-boosting compensation topology with double pole-zero cancellation (ACBC-DPZ) for a multistage amplifier driving a very large capacitive load. The proposed technique modifies the original AC-boosting compensation (ACBC) topology to increase the power-bandwidth efficiency and reduce the size for the output power transistor and compensation capacitor. Simulation results show that the ACBC-DPZ amplifier using a CSM 0.18 μm CMOS process can achieve a unity gain bandwidth of 14 MHz and an average slew rate of 3.88 V/μs at 1500 pF load. The amplifier dissipates 2.55 mW at a 1.8 V supply.     

Improved triangular voltage sweep (TVS) technique for measurement of ionic charge in MOS structures

The sensitivity and accuracy of the conventional TVS technique is influenced by a capacitive current associated with the MOS capacitor which is superimposed on the ionic current. The authors present a new method and measuring circuit for automatic compensation of the capacitive current at the input of the current measuring instrument.<>     

调容式自动补偿装置在低压电网的分析与仿真

研究和分析了调容式自动补偿装置发展现状和存在的问题。说明了其工作原理、硬件和软件设计方案。调容式消弧线圈的设计是基于DSPTMS320F2812控制可控硅开关电容器,通过实验验证了在系统发生单相接地时,动态快速跟踪,自动补偿接地点电容电流,达到消弧的目的。     

一种采用共栅频率补偿的轨到轨输入/输出放大器

提出了一种采用共栅频率补偿的轨到轨输入/输出放大器,与传统的Miller补偿相比,该放大器不仅可以消除相平面右边的低频零点,减少频率补偿所需要的电容,还可获得较高的单位增益带宽.所提出的放大器通过CSMC 0.6μm CMOS数模混合工艺进行了仿真设计和流片测试:当供电电压为5V,偏置电流为20μA,负载电容为10pF时,其功耗为1.34mW,单位增益带宽为25MHz;当该放大器作为缓冲器,供电电压为3V,负载电容为150pF,输入2.66 Vpp10kHz正弦信号时,总谐波失真THD为-51.6dB.     

高压钠灯单灯补偿线路功率因数分析

本文推导出高压钠灯线路补偿电容容量精算公式,分析讨论了高压钠灯电参数离散和寿命期间漂移将导致电路功率因数过补,线路呈现容抗性。指出高压钠灯线路补偿电容选择,应防止过多的负补。这对理解高压钠灯电路无功补偿和补偿电容量的选用,具有重要的指导意义。     

Bipolar Current Feedback Amplifier: Compensation Guidelines

The aim of the paper is to discuss in detail the compensation of the current feedback amplifier (CFOA). The approach is suitable for a pencil-and-paper compensation and takes into account both resistive and capacitive feedback. The frequency limitation inside the CFOA and due to a load capacitor are also considered. The feature of the CFOA which can be simply compensated for when it is configured as a differentiator is also exploited. To validate the proposed strategies, Spice simulations were performed on the fundamental CFOA topologies, and some of them are included and discussed in the paper.     

Three-stage large capacitive load amplifier withdamping-factor-control frequency compensation

A novel damping-factor-control frequency compensation (DFCFC) technique is presented in this paper with detailed theoretical analysis, This compensation technique improves frequency response, transient response, and power supply rejection for amplifiers, especially when driving large capacitive loads, Moreover, the required compensation capacitors are small and can be easily integrated in commercial CMOS process. Amplifiers using DFCPC and nested Miller compensation (NMC) driving two capacitive loads, 100 and 1000 pF, were fabricated using a 0.8-μm CMOS process with V_tn=0.72 V and V_tp=-0.75 V. For the DFCFC amplifier driving a 1000-pF load, a 1-MHz gain-bandwidth product, 51° phase margin, 0.33-V/μs slew rate, 3.54-μs settling time, and 426-μW power consumption are obtained with integrated compensation capacitors. Compared to the NMC amplifier, the frequency and transient responses of the DFCFC amplifier are improved by one order of magnitude with insignificant increase of the power consumption     

A New Method Modifying Single Miller Feedforward Frequency Compensation to Drive Large Capacitive Loads: Putting an Attenuator in the Path

A new method to compensate three-stage amplifier to drive large capacitive loads is proposed in this paper. Gain Bandwidth Product is increased due to use an attenuator in the path of miller compensation capacitor. Analysis demonstrates that the gain bandwidth product will be improved significantly without using large compensation capacitor. Using a feedforward path is deployed to control a left half plane zero which is able to cancel out first non-dominant pole. A three stage amplifier is simulated in a 0.18 μm CMOS technology. The purpose of the design is to compensate three-stage amplifier loading 1000 pF capacitive load. The simulated amplifier with a 1000 pF capacitive load is performed in 3.3 MHz gain bandwidth product, and phase margin of 50. The compensation capacitor is reduced extremely compared to conventional nested miller compensation methods. Since transconductance of each stage is not distinct, and it is close to one another; as a result, this method is suitable low power design methodology.     

电感补偿高方向性的微带定向耦合器

定向耦合器作为一种重要的微波元件在微波电路与微波集成电路中有着广泛的应用。在传统的微带线定向耦合器设计中,奇偶模之间不同的相位速度导致了较低的隔离度。目前提高方向性的手段大多采用电容加载或者再注入的补偿手段,其实现方式均属于对相位速度的补偿。介绍了一种采用对称的电感加载结构进行相位速度补偿的微带线定向耦合器,为了提高微带定向耦合器的方向性,通过对微带线定向耦合器的4个端口进行感性加载,实现了微带定向耦合器窄带的低损耗和高方向性的电气指标,通过实物制作与测试,证明了方法可以实现。     

极点跟随的LDO稳压器频率补偿方法

提出了一种新型的用于LDO稳压器的频率补偿方法,并通过动态偏置电压缓冲器进行了电路实现。该方法提供了快速的瞬态响应,且无需芯片上频率补偿电容,提高了芯片的集成度。理论分析与仿真结果表明,LDO稳压器在满负载条件下的频率稳定得到了保证。     

Three-Stage CMOS OTA for Large Capacitive Loads With Efficient Frequency Compensation Scheme

A simple compensation strategy, which employs passive components only, is adopted to design a three-stage operational transconductance amplifier (OTA) suitable for driving high capacitive loads. Compared to the classical nested Miller compensation technique, the new solution exploits two additional resistors and allows a reduction in the values of the compensation capacitors of about an order of magnitude. The OTA was fabricated using 0.35-mum CMOS technology and exhibits a 1.4-MHz gain-bandwidth with a load of 500 pF     

共源共栅两级运放的三种补偿结构分析和比较

提出了三种应用于两级CMOS运算放大器的米勒电容补偿结构,分析了三种结构的小信号等效电路,得到传递函数和零点、极点的位置,以此分析和实现三种结构的频率补偿。其中两种共源共栅米勒补偿结构与直接米勒补偿结构相比,能用更小的芯片面积实现更优的运放性能,得到更大的单位增益带宽积和相位裕度,实现更好的频率特性。通过使用0.18μm CMOS工艺对电路进行仿真,结果验证了共源共栅米勒补偿技术的优越性。     

Embedded capacitor multiplier gain boosting compensation for large-capacitive-load three-stage amplifier with slew rate enhancement

An embedded capacitor multiplier gain boosting compensation (ECMGBC) technique with slew rate enhancement circuit is presented in this paper for a three-stage amplifier. The ECMGBC technique pushes the non-dominant complex poles of the amplifier to high frequencies for gain-bandwidth product (GBW) extension under low quiescent current. In addition, the proposed slew rate enhancement circuit improves the transient responses of ECMGBC amplifier without any problem of oscillation. The ECMGBC amplifier has been designed and simulated in a 0.35-µm mixed signal CMOS process. From the post-simulation results, the amplifier driving a 1,000-pF capacitance achieves a 1-MHz GBW with a phase margin of 60° by consuming 13.5-µA quiescent current. The total compensation capacitance is only 1.2 pF. The transient responses are simulated when the amplifier is in unity-gain non-inverting configuration with a 0.6-V step input at a 2-V supply. The 1 % settling time is 1.1 µs for a 1,000-pF load capacitance. Compared with previously reported works, the ECMGBC amplifier achieves good figures of merit. Moreover, the ECMGBC amplifier obtains a very high ratio of load capacitance to total compensation capacitance.