Effects of rapid thermal annealing on nitrided gate oxide grown on 4H-SiC

The electrical characteristics of thermally nitrided gate oxides on n-type 4H-SiC, with and without rapid thermal annealing processes, have been investigated and compared in this paper. The effects of annealing time (isothermal annealing) and annealing temperature (isochronal annealing) on the gate oxide quality have also been systematically investigated. After rapid isothermal and isochronal annealings, there has been a significant increase in positive oxide-charge density and in oxide-breakdown time. A correlation between the density of the positive oxide charge and the oxide breakdown reliability has been established. We proposed that the improvement in the oxide-breakdown reliability, tested at electric field of 11 MV/cm, is attributed to trapping of injected electron by the positive oxide charge and not solely due to reduction of SiC-SiO₂ interface-trap density.     

SIMS analysis of nitrided oxides grown on 4H-SiC

This paper shows for the first time, physical evidence of nitrogen incorporation at the oxide-SiC interface as a result of post-oxidation annealing in nitric oxide (NO). Using secondary ion mass spectroscopy (SIMS) analysis, the location and shape of the nitrogen profile is seen to be almost identical to that found in oxide-silicon interfaces. Close examination of oxygen and carbon SIMS profiles and atomic force microscope scans also indicate a sharper interface when annealing is done using NO compared to inert gases such as N₂ or argon, possibly due to the removal of carbon clusters which form at the interface during oxidation. As in the case of silicon, NO annealing shows great promise as a processing step in the production of device quality gate oxides on SiC.     

4H-SiC表面热氧化生长SiOx薄膜特性的研究

采用扫描电子显微镜（SEM）、原子力显微镜（AFM）和X射线光电子能谱（XPS）测试方法对4H-SiC上热氧化生长的氧化硅（SiOx）薄膜表面形貌进行观测,并分析研究SiOx薄膜和SiOx/4H-SiC界面的相关性质,包括拟合Si2p、O1s和C1s的XPS谱线和分析其相应的结合能,以及分析SiOx层中各主要元素随不同深度的组分变化情况,从而获得该热氧化SiOx薄膜的化学组成和化学态结构,并更好地了解其构成情况以及SiOx/4H-SiC的界面性质。     

Conduction mechanisms in MOS gate dielectric films

This paper reviews the conduction mechanisms in the gate dielectric films of MOSFETs for VLSI and ULSI technologies. They include Fowler–Nordheim tunneling, internal Schottky (or Pool–Frenkel) effect, two-step (or trap-assisted) tunneling, shallow-trap-assisted tunneling, and band-to-band tunneling. The current transport in the gate dielectric films is manly controlled by film material composition, film processing conditions, film thickness, trap energy level and trap density in the films. In general, for a given gate dielectric film, the current transport behaviors are normally governed by one or two conduction mechanisms.     

Influence of dry and wet cleaning on the properties of rapid thermal grown and deposited gate dielectrics

Various silicon surface cleaning processes for rapid thermal in-situ polysilicon/ oxide/silicon stacked gate structures have been evaluated. Metal-oxide-semiconductor capacitors were fabricated to assess the effects of cleaning on the quality of gate oxide structures produced by both rapid thermal oxidation (RTO) and rapid thermal chemical vapor deposition (RTCVD). Excellent electrical properties have been achieved for both RTO and RTCVD gate oxides formed on silicon wafers using either an ultraviole/zone (UV/O₃) treatment or a modified RCA clean. On the contrary, poor electrical properties have been observed for RTO and RTCVD gate oxides formed on silicon wafers using a high temperature bake in Ar, H₂, or high vacuum ambient. It has also been found that the electrical properties of the RTCVD gate oxides exhibit less dependence upon cleaning conditions than those of RTO gate oxides. This work demonstrates that initial surface condition prior to gate oxide formation plays an important role in determining the quality of RTO and RTCVD gate oxides.     

Quality of gate oxides grown on state-of-the-art SIMOX and ZMR SOIsubstrates

The quality of 25-nm gate oxides formed on state-of-the-art SIMOX and ZMR silicon-on-insulator (SOI) substrates was studied using NMOSFETs. Circular, edgeless, and conventional island isolated devices were used. Devices fabricated on bulk silicon wafers were studied for comparison. I-V characteristics, breakdown voltages, charge trapping, and charge to breakdown were characterized. The results clearly demonstrated that the quality of SIMOX and ZMR wafers and especially of the top Si surface was as good as that of bulk silicon. The quality of the gate oxides formed on island isolated devices was poor due to defective oxide formed on the sidewalls. A comparison of circular, edgeless MOSFETs and island isolated MOSFETs can be used to optimize island etching, sidewall cleaning, and gate oxidation processes     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

Half-bridge inverter using 4H-SiC gate turn-off thyristors

This paper reports on the first demonstration of a half-bridge power inverter constructed from silicon carbide gate turn-off thyristors (GTOs) operated in the conventional GTO mode. This circuit was characterized with input bus voltages of up to 600 VDC and 2 A (peak current density of 540 A/cm²) with resistive loads using a pulse-width modulated switching frequency of 2 kHz. We discuss the implications of the thyristor's electrical characteristics and the circuit topology on the overall operation of the half-bridge circuit. This work has determined the conservative critical rate of rise value of the off-state voltage to be 200 V/μs in these devices     

Inductive switching of 4H-SiC gate turn-off thyristors

The high-temperature operation of a silicon carbide gate turn-off thyristor is evaluated for use in inductively loaded switching circuits. Compared to purely resistive load elements, inductive loads subject the switching device to higher internal power dissipation. The ability of silicon carbide components to operate at elevated temperatures and high power dissipations are important factors for their use in future power conversion/control systems. In this work, a maximum current density of 540 A/cm² at 600 V was switched at a frequency of 2 kHz and at several case temperatures up to 150°C. The turn-off and turn-on characteristics of the thyristor are discussed     

Ultrathin aluminum oxide gate dielectric on N-type 4H-SiC prepared by low thermal budget nitric acid oxidation

MOS capacitors with an ultrathin aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric were fabricated on n-type 4H-SiC. Al/sub 2/O/sub 3/ was prepared by room-temperature nitric acid (HNO/sub 3/) oxidation of ultrathin Al film followed by furnace annealing. The effective dielectric constant of k/spl sim/9.4 and equivalent oxide thickness of 26 /spl Aring/ are produced, and the interfacial layer and carbon clusters are not observed in this paper. The electrical responses of MOS capacitor under heating and illumination are used to identify the conduction mechanisms. For the positively biased case, the conduction mechanism is shown to be dominated by Schottky emission with an effective barrier height of 1.12/spl plusmn/0.13 eV. For the negatively biased case, the gate current is shown to be due to the generation-recombination process in depletion region and limited by the minority carrier generation rate. The feasibility of integrating alternative gate dielectric on SiC by a low thermal budget process is demonstrated.     

Advantages of thermal nitride and nitroxide gate films in VLSI process

Thin gate SiO2films thinner than 200 Å often deteriorate throughout developmental VLSI processes, including refractory metal or silicide gates and ion- or plasma-assisted processes. Thermal nitridation of such SiO2films improves the MOS characteristics by producing surface protective layers against impurity penetration and by producing good interfacial characteristics. This fact indicates that a thermally grown silicon nitride film on a silicon substrate is the most promising candidate for a very-thin gate insulator. Experimental data show significant benefits from the nitride film for future VLSI devices.     

Wet or dry ultrathin oxides: impact on gate oxide and device reliability

In this study, wet and dry oxidation processes for 3.5 nm ultrathin dielectrics are compared in terms of oxide and device reliability. It is demonstrated that a wet oxidation enables to strongly improve the oxide lifetime. On the contrary, the device reliability has been found to be slightly affected by the process choice. Finally, these results associated with charge pumping and stress induced leakage current measurements indicate that the bulk oxide, more than the Si/SiO₂ interface, is affected by the growth process ambience (wet or dry oxidation).     

Rapid thermal anneal of gate oxides for low thermal budget TFT's

The performance and reliability of deposited gate oxides for thin film transistors (TFT's) has been studied as a function of rapid thermal annealing (RTA) conditions. The effect of temperature ranging from 700 to 950°C and the annealing ambients including oxygen (O₂), argon (Ar), and nitrous oxide (N₂O) is investigated. Improvement in charge to breakdown (Q_bd) is seen starting from 700°C, with marked increase at 900°C temperature and above. The N₂O and Ar ambients result in higher Q_bd compared to O₂ ambient and we attribute this to reduced interfacial stress. Fourier Transform Infrared spectroscopy (FTIR) is used to qualitatively measure the stress. The bias temperature instability is decreased by RTA. The TFT characteristics are significantly improved with RTA gate oxide. The RTA-Ar anneal at 950°C results in the lowest trap density in TFT's as measured from charge pumping technique     

Micropipe and dislocation density reduction in 6H-SiC and 4H-SiC structures grown by liquid phase epitaxy

We investigated silicon carbide (SiC) epitaxial layers grown by liquid phase epitaxy (LPE). The layers were grown on 6H-SiC and 4H-SiC well-oriented (0001) 35 mm diameter commercial wafers as well as on 6H-SiC Lely crystals. A few experiments were also done on off-axis 6H-SiC and 4H-SiC substrates. Layer thickness and growth rate ranged from 0.5 to 50 microns and 0.5 to 10 μm/h, respectively. Layers were investigated by x-ray diffraction, x-ray topography, and selective chemical etching in molten KOH. It was found that dislocation and micropipe density in LPE grown epitaxial layers were significantly reduced compared with the defect densities in the substrates.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

High-purity semi-insulating 4H-SiC grown by the seeded-sublimation method

The growth of high-purity, semi-insulating (HPSI) 4H-SiC crystals has been achieved using the seeded-sublimation growth technique. These semi-insulating (SI) crystals (2-inch diameter) were produced without the intentional introduction of elemental deep-level dopants, such as vanadium, and wafers cut from these crystals possess room-temperature resistivities greater than 10⁹ Ωcm. Based upon temperature-dependent resistivity measurements, the SI behavior is characterized by several activation energies ranging from 0.9–1.5 eV. Secondary ion mass spectroscopy (SIMS) and electron paramagnetic resonance (EPR) data suggest that the SI behavior originates from deep levels associated with intrinsic point defects. Typical micropipe densities for wafers were between 30 cm⁻² and 150 cm⁻². The room-temperature thermal conductivity of this material is near the theoretical maximum of 5 W/m K for 4H-SiC, making these wafers suitable for high-power microwave applications.     

Improvement in performance and degradation characteristics ofMOSFETs with thin gate oxides grown at high temperature

A study of the effect of gate oxide growth temperature on the performance and degradation of MOSFETs with thin (~11 nm) gate oxides is reported. Channel mobility for electrons and holes is observed to increase with the increase in the oxidation temperature (800 to 1100°C). Degradation of on-state and off-state parameters resulting from channel hot-carrier stress is investigated. A good correlation is observed between the degradation of device parameters and interface state generation. It is found that the interface hardness to hot-carrier stress is higher in the MOSFETs with gate oxides grown at higher temperatures     

700-V asymmetrical 4H-SiC gate turn-off thyristors (GTO's)

Silicon Carbide (4H-SiC), asymmetrical gate turn-off thyristors (GTO's) were fabricated and tested with respect to forward voltage drop (V_F), forward blocking voltage, and turn-off characteristics. Devices were tested from room temperature to 350°C in the dc mode. Forward blocking voltages ranged from 600-800 V at room temperature for the devices tested. V_F of a typical device at 350°C was 4.8 V at a current density of 500 A/cm². Turn-off time was less than 1 μs. Although no beveling or advanced edge termination techniques were used, the blocking voltage represented approximately 50% of the theoretical value when tested in an air ambient. Also, four GTO cells were connected in parallel to demonstrate 600-V, 1.4 A (800 A/cm ²) performance     

Patterning by rapid thermal annealing of GaAs layers grown on diluted nitride QWs

The structural characterization of hole patterns on GaAs cap layers grown on GaInNAs quantum wells (QWs) created by rapid thermal annealing is shown in this work. The effect of annealing temperature on the hole size, as well as the impact of the ion density present during the growth of the QW on the formation of this hole pattern, is presented. Structural (atomic force, scanning electron and transmission electron microscopy) and optical characterization (cathodoluminescence) of the samples is presented. The structure of the planes forming the walls and base of these holes is proposed.     

Study of thin gate oxides grown in an ultra-dry/clean triple-wall oxidation furnace system

A triple-wall oxidation furnace system has been designed and implemented successfully. This paper explains the system in detail and discusses the reliability of the gate oxides grown in such a system. The 9.3 nm gate oxides display an improved dielectric breakdown field strength (15 MV/cm), and charge-to-breakdown (45C/cm²) with less interface trap generation than the gate oxides grown in a conventional single-wall oxidation system. From these results, we conclude the microscopic defects as well as the macroscopic defects are better controlled in a triple-wall oxidation system than in a conventional single-wall oxidation system. This new system permits the study of the Si-SiO₂ interface with a control on the number of electronic defects inherent in the processing of MOS devices.