Breakdown characteristics of nFETs in inversion with metal/HfO2 gate stacks

Time zero and time dependent dielectric breakdown (TZBD and TDDB) characteristics of atomic layer deposited (ALD) TiN/HfO₂ high-κ gate stacks are studied by applying ramped and constant voltage stress (RVS and CVS), respectively, on the n-channel MOS devices under inversion conditions. For the gate stacks with thin high-κ layers (?3.3 nm), breakdown (BD) voltage during RVS is controlled by the critical electric field in the interfacial layer (IL), while in the case of thicker high-κ stacks, BD voltage is defined by the critical field in the high-κ layer. Under low gate bias CVS, one can observe different regimes of the gate leakage time evolution starting with the gate leakage current reduction due to electron trapping in the bulk of the dielectric to soft BD and eventually hard BD. The duration of each regime, however, depends on the IL and high-κ layer thicknesses. The observed strong correlation between the stress-induced leakage current (SILC) and frequency-dependent charge pumping (CP) measurements for the gate stacks with various high-κ thicknesses indicates that the degradation of the IL triggers the breakdown of the entire gate stack. Weibull plots of time-to-breakdown (T_BD) suggest that the quality of the IL strongly affects the TDDB characteristics of the Hf-based high-κ gate stacks.     

Reliability of advanced high-k/metal-gate n-FET devices

Hot-carrier degradation and bias-temperature instability of FinFET and fully-depleted SOI devices with high-k gate dielectrics and metal gates are investigated. Thinner SOI results in increased hot-carrier degradation, which can be recovered by junction engineering. FinFETs with (1 1 0) Si active surfaces exhibit degradation of sub-threshold swing after hot carrier stress, indicating generation of interface states. The effect of duty cycle on bias-temperature instability modulates the quasi-steady-state trap occupancy over a broad distribution of electron trapping and de-trapping times. Only the deeper traps remain filled for low duty cycle, and shallower traps are emptied during AC stress.     

A semi-empirical analytic model for threshold voltage instability in MOSFETs with high-k gate stacks

n the threshold voltage and the induced trap density. The obtained model is also verified by extensive experimental data of trapping and de-trapping stress from different high-k gate configurations.     

Analytical Low Frequency NBTI Compact Modeling with H<Subscript>2</Subscript> Locking and Electron Fast Capture and Emission

Besides reaction-diffusion theory explaining the generation and passivation of interface trap (ΔN_IT), hole trapping/de-trapping in preexisting gate insulator traps and transient charge occupancy in ΔN_IT are also combined to describe the characteristic of NBTI degradation. However, it is found that H₂ locking effect and Electron Fast Capture/Emission play key roles in the NBTI degradation. In this paper, an analytical low frequency AC NBTI compact model has been proposed to accurately predict the shift in threshold voltage. Two fitting parameters (α and F_FAST) have been introduced to account for the H₂ locking and fast electron capture and emission. The comparison between the proposed model and the experimental data has been carried out, and the results show that our proposed can catch the kinetics of NBTI degradation under low frequency AC stress conditions.     

Pre- and post-BD electrical conduction of stressed HfO2/SiO2 MOS gate stacks observed at the nanoscale

In this work, the electrical properties of fresh and stressed HfO₂/SiO₂ gate stacks have been studied using a prototype of Conductive Atomic Force Microscope with enhanced electrical performance (ECAFM). The nanometer resolution of the technique and the extended current dynamic range of the ECAFM has allowed to separately investigate the effect of the electrical stress on the SiO₂ and the HfO₂ layer of the high-k gate stack. In particular, we have investigated this effect on both layers when the structures where subjected to low and high field stresses.     

Probing stress effects in HfO2 gate stacks with time dependent measurements

Effects of constant voltage stress (CVS) on gate stacks consisting of an ALD HfO₂ dielectric with various interfacial layers were studied with time dependent sensing measurements: DC I–V, pulse I–V, and charge pumping (CP) at different frequencies. The process of injected electron trapping/de-trapping on pre-existing defects in the bulk of the high-κ film was found to constitute the major contribution to the time dependence of the threshold voltage (V_t) shift during stress. The trap generation observed with the low frequency CP measurements is suggested to occur within the interfacial oxide layer or the interfacial layer/high-κ interface, with only a minor effect on V_t.     

A finite weakest-link model of lifetime distribution of high-k gate dielectrics under unipolar AC voltage stress

This paper presents a new probability distribution function for the breakdown lifetime of high-k gate dielectrics under unipolar AC voltage stress. This function is derived from a finite weakest-link model, where the gate oxide layer is considered to consist of many potential breakdown cells. Each potential breakdown cell is modeled as a series coupling of several subcells, which is analogous to the fiber-bundle model for the strength statistics of structures. The present model indicates that the type of lifetime distribution varies with the gate area and the dependence of the mean lifetime on the gate area deviates from the classical Weibull scaling law. It is shown that the model agrees well with the observed lifetime histograms of HfO₂ based gate dielectrics under unipolar AC voltage stress.     

Carrier separation analysis for clarifying carrier conduction and degradation mechanisms in high-k stack gate dielectrics

The carrier conduction and the degradation mechanism in n⁺gate p-channel metal-insulator-semiconductor field-effect-transistors with HfAlO_X (Hf: 60 at.%, Al: 40 at.%)/SiO₂ dielectric layers have been investigated using carrier separation method. Since gate current depends on substrate bias and both electron and hole currents are independent of temperature over the range of 25–150 °C, the conduction mechanism for both currents is controlled by a tunneling process. As the interfacial SiO₂ layer (IL) thickness increases in a fixed high-k layer thickness (T_high-k), a dominant carrier in the leakage current changes from hole to electron around 2.2-nm-thick IL. This is due to an asymmetric barrier height for electrons and holes at the SiO₂/Si interface. On the contrary, in the case of a fixed IL thickness of 1.3 nm, the hole current is dominant in the leakage current, regardless of T_high-k. It is shown that the dominant carrier in the leakage current depends on the structure of the high-k stack. Both electron and hole currents for the stress-induced-leakage-current (SILC) state increase slightly relative to the initial currents, which means that the trap generation in the high-k stack occurs near both the conduction band edge of n⁺poly-Si gate and the valence band edge of Si substrate. The electron current at soft breakdown (SBD) state dramatically increases over that for the SILC state, while the hole currents for both the SILC state and SBD are almost the same. This indicates that the defect sites generated in the high-k stack after SBD are located at energies near the conduction band edge of n⁺poly-Si gate. Both the defect generation rate and the defect size in the HfAlO_X/SiO₂ stacks are large compared with those in SiO₂. It is inferred that, in high-k dielectric stack, the defect generation mainly occurs in the high-k side rather than the IL side, and the defect size larger than the case of SiO₂ could be related to a larger dielectric constant of the high-k layer.     

Applications of DCIV method to NBTI characterization

The DCIV method was applied to investigate negative bias temperature instability (NBTI) in SiO₂ gate oxides. The DCIV technique, which measures the interface defect density independently from bulk oxide charges, delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift, ΔV_TH. The DCIV results obtained during both stress and relaxation phases are generally consistent with the main features of the reaction–diffusion (R–D) model, which suggests positive charge generation/annealing at the Si/SiO₂ interface due to breaking/re-passivation of the Si–H bonds. These results are in agreement with the spin-dependent recombination (SDR) experiments, which reflect the density of the Si dangling bonds at the Si/SiO₂ interface (P_b centers) and its vicinity (E′ centers). Comparison of degradation kinetics as measured by DCIV, charge-pumping, and I_D − V_G (ΔV_TH) techniques, however, suggests that ΔV_TH includes additional contributions, most likely from the oxide bulk charges. For comparison, an NBTI study was also performed on the high-k HfO₂/SiO₂ gate stacks. After adjusting for the high-k related contribution, similar kinetics of the long-term stress interface trap generation was observed in SiO₂ and high-k gate stacks suggesting a common mechanism of the interface degradation.     

Temperature dependent time-to-breakdown (TBD) of TiN/HfO2 n-channel MOS devices in inversion

Effect of temperature on time-to-breakdown (T_BD) of n⁺-ringed n-channel MOS capacitors with atomic layer deposited TiN/HfO₂ based gate stacks is studied. While interfacial layer (IL) growth condition and thickness varied the high-κ layer thickness and processing was unchanged. These devices were investigated by applying a constant voltage stress (CVS) in inversion (substrate injection) at room and elevated temperatures. For high electric fields (10-15 MV/cm) across IL, it is observed that T_BD is thermally activated irrespective of IL condition. Activation energies (2-3 eV after correction), found from Arrhenius plots of T_BD for different IL conditions, show good matches with those associated with field-driven thermochemical model of breakdown developed for SiO₂.     

Recent advances and current challenges in the search for high mobility band-edge high-k/metal gate stacks

Continued miniaturization of the different physical elements of a Si MOSFET required in order to attain higher transistor performance and greater economies of scale have spurred the need for significant materials innovations. This is most apparent in the search for the ideal high-k/Metal Gate stack that would replace conventional SiON/Poly-Si gate stacks. In this paper, we will review some of the recent advances and remaining challenges for high-k/Metal Gate stacks. It is shown that significant progress has been made towards improving electron mobility in HfO₂/Metal Gate stacks by a combination of high temperature processes, nitrogen free interfaces and optimized metal deposition processes which result in mobility values competitive with SiON/Poly-Si. In addition by inserting nanoscale layers that comprise strongly electropositive gp. IIA and IIIB elements in between the HfO₂and metal electrode stack have resulted in high mobility, band-edge aggressively scaled High-k/Metal Gate stacks. While much progress has been made with nMOSFET stacks, it will also be shown that a number of roadblocks remain with obtaining a similar solution for pMOSFET stacks, primarily due to the presence of thermally activated oxygen vacancies that induce large negative threshold voltage shifts towards midgap in HfO₂/high workfunction metal stacks.     

HfAlOx high-k gate dielectric on SiGe: Interfacial reaction, energy-band alignment, and charge trapping properties

Ultra thin HfAlO_x high-k gate dielectric has been deposited directly on Si_1−xGe_x by RF sputter deposition. The interfacial chemical structure and energy-band discontinuities were studied by using X-ray photoelectron spectroscopy (XPS), time of flight secondary ion mass spectroscopy (TOF-SIMS) and electrical measurements. It is found that the sputtered deposited HfAlO_x gate dielectric on SiGe exhibits excellent electrical properties with low interface state density, hysteresis voltage, and frequency dispersion. The effective valence and conduction band offsets between HfAlO_x (E_g = 6.2 eV) and Si_1−xGe_x (E_g = 1.04 eV) were found to be 3.11 eV and 2.05 eV, respectively. In addition, the charge trapping properties of HfAlO_x/SiGe gate stacks were characterized by constant voltage stressing (CVS).     

Gate oxide wear out using novel polysilazane-base inorganic as nano-scaling shallow trench filling

The phenomenon of floating gate (FG) crystallization and extrinsic gate oxide breakdown (V_bd) are discussed using polysilazane-base inorganic material SOD (Spin-On-Dielectric) as shallow trench isolation (STI) filling for 50 nm flash memory fabrication. The pinholes are found along the FG grain boundary in wide active regions because of tensile stress induced by SOD material in STI process, thus gate oxide wears out by following wet cleaning steps. The chemical oxide formation during FG deposition can effectively inhibit gate oxide early breakdown. Moreover, FG sheet resistance (R_s) in 550 °C/air deposition condition can significantly reduce about 20% in comparison with 520 °C/O₂ and 400 °C/N₂ conditions.     

The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals

We demonstrate the possibility to control charge trapping in the memory stacks comprised of metal nanocrystals (NCs) sandwiched between SiO₂ and high-k dielectric films by light irradiation. Non-equilibrium depletion effects in the state of the art charge trapping memories are reported for the first time. The studied nonvolatile memory devices employ Au NCs, thermal SiO₂ tunnel layer, atomic layer deposited HfO₂ blocking layer and Au/Pt metal gate. The memory windows are 3 V and 10.5 in the dark and under illumination for ±10 V programming voltages. Reliability limitations of the studied structure, in particular leakage currents and effects in high electric fields have been investigated in detail and are discussed in view of the mentioned device application. Low programming voltages and currents, and high light sensitivity make suggested NVM structures promising for developing digital imagers with ultra-low power consumption.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Reliability characteristics of high-k dielectrics

In this paper, recent results of Weibull slopes, area scaling factors, and breakdown behaviors observed for both soft breakdown and hard breakdown are discussed. These results would help to shed light on the breakdown mechanism of HfO₂ gate dielectrics. The Weibull slope β of the hard breakdown for both the area dependence and the time-to-dielectric-breakdown distribution was found to be β=2, whereas that of the soft breakdown was about 1.4 (EOT=14 Å). We also integrated the time-to-breakdown characteristics of HfO₂ under unipolar AC voltage stress on MOS capacitors. The results show that longer lifetime of HfO₂ has been observed when compared to constant voltage stress. Higher frequency and lower duty cycle in the AC stress resulted in longer lifetime. As thickness decreases, the amount of lifetime enhancement decreases. The enhancement of unipolar t_BD is attributed to less charge trapping during the “on time”, t_on and charge detrapping during the off time, t_off. It is proposed that time (τ_in) for charge to be trapped in HfO₂ is longer than t_on of unipolar stress under high frequency. In addition to experimental results, possible solutions are discussed.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Reliability of SiO2 and high-k gate insulators: A nanoscale study with conductive atomic force microscopy

In this work, a conductive atomic force microscope (C-AFM) is used to study the reliability (degradation and breakdown, BD) of SiO₂ and high-k dielectrics. The effect of a current limit on the post-BD SiO₂ electrical properties at the nanoscale is discussed. In particular, the impact of a current limit imposed during the stress on the post-BD oxide conductivity at the position where BD has been triggered, the area affected by the BD event and the structural damage induced in the broken down region will be investigated. A purposely developed C-AFM with enhanced electrical performance (ECAFM) is also presented, which has been used for the electrical characterization of HfO₂/SiO₂ gate stacks. The conduction of the fresh (without stress), electrically stressed and broken down stacks have been analyzed.     

Charge carrier generation/trapping mechanisms in HfO2/SiO2 stack

We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness T_phy) hafnium oxide (HfO₂)/silicon dioxide (SiO₂) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).     

Temperature and voltage dependences of the capture and emission times of individual traps in high-k dielectrics

Quantized threshold voltage (VTH) relaxation transients are observed in nano-scaled field effect transistors (FETs) after bias temperature stress. The abrupt steps are due to trapping/detrapping of individual defects in the gate oxide and indicate their characteristic emission/capture times. Individual traps are studied in n-channel SiO₂/HfSiO FETs after positive gate stress to complement previous studies performed on SiO(N). Similarly to single SiO(N) traps, strong thermal and bias dependences of the emission and capture times are demonstrated. The high-k traps have a higher density but a reduced impact on VTH due to their separation from the channel.