Low-energy GALS NoC with FIFO—Monitoring dynamic voltage scaling

In this paper we propose two dynamic voltage scaling (DVS) policies for a GALS NoC, which is designed based on fully asynchronous switch architectures. The first one is a history-based DVS policy, which exploits the link utilization and adjusts the voltages of different parts of the router among a few voltage levels. The second one is a FIFO-adaptive DVS, which uses two FIFO threshold levels for decision making. It judiciously adjusts supply voltage of each switch among only three voltage levels. The introduced architecture is simulated in 90 nm CMOS technology with accurate Spice simulations. Experimental results show that the FIFO-adaptive DVS not only lowers the implementation cost, but also in a 86 % saturated network achieves 36 % energy-delay product (ED) saving compared to the DVS policy based on link utilization.     

电压调节技术用于SoC低功耗设计

针对便携设备在SOC系统设计中的功耗问题，通过电压调节和电压控制的方法来达到降低功耗的目的。可以用两种方法来实现，一种是开环电压调节(动态)，另一种是闭环(自适应)电压控制的方法。     

Reward-based voltage scheduling for dynamic-priority hard real-time systems

Reward-based scheduling has been investigated for flexible applications in which an approximate but timely result is acceptable. Meanwhile, significant research efforts have been made on voltage scheduling which exploits the tradeoff between the processor speed and the energy consumption. In this paper, we address the combined scheduling problem of maximizing the total reward of hard real-time systems with a given energy budget. We present an optimal off-line algorithm and an efficient on-line algorithm for jobs with their own release-times/deadlines under Earliest-Deadline-First (EDF) scheduling. Experimental results show that the solution computed by the on-line algorithm is no more than 14% worse than the theoretical optimal solution obtained by the optimal off-line algorithm. This research was supported by the MIC (Ministry of Information and Communication), Korea, under the ITRC (Information Technology Research Center) support program supervised by the IITA (Institute of Information Technology Assessment). A preliminary version of this article was presented at Real-Time and Embedded Computing Systems and Applications (RTCSA’04).     

A miniature high-efficiency fully digital adaptive voltage scaling buck converter

A miniature high-efficiency fully digital adaptive voltage scaling (AVS) buck converter is proposed in this paper. The pulse skip modulation with flexible duty cycle (FD-PSM) is used in the AVS controller, which simplifies the circuit architecture (<170 gates) and greatly saves the die area and the power consumption. The converter is implemented in a 0.13-μm one-poly-eight-metal (1P8 M) complementary metal oxide semiconductor process and the active on-chip area of the controller is only 0.003 mm², which is much smaller. The measurement results show that when the operating frequency of the digital load scales dynamically from 25.6 MHz to 112.6 MHz, the supply voltage of which can be scaled adaptively from 0.84 V to 1.95 V. The controller dissipates only 17.2 μW, while the supply voltage of the load is 1 V and the operating frequency is 40 MHz.     

Temperature-adaptive voltage scaling for enhanced energy efficiency in subthreshold memory arrays

Static random access memory (SRAM) circuits optimized for minimum energy consumption typically operate in the subthreshold regime with ultra low-power-supply voltages. Both the read and the write propagation delays of a subthreshold memory circuit are significantly reduced with an increase in the die temperature. The excessive timing slack observed in the clock period of constant-frequency subthreshold memory circuits at elevated temperatures provides new opportunities to lower the active-mode energy consumption. Temperature-adaptive dynamic supply voltage tuning (TA-DVS) technique is proposed in this paper to reduce the high-temperature energy consumption of ultra low-voltage subthreshold SRAM arrays. Results indicate that the energy consumption can be lowered by up to 32.8% by dynamically scaling the supply voltage at elevated temperatures. The impact of the temperature-adaptive dynamic supply voltage scaling technique on the data stability of the subthreshold SRAM bit-cells is presented. The effectiveness of the TA-DVS technique under process parameter and supply voltage variations is evaluated. An alternative technique based on temperature-adaptive reverse body bias (TA-RBB) to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption characteristics of the two temperature-adaptive voltage tuning techniques are compared.     

Sensor based adaptive voltage scaling on FPGAs: Calibration and parametrization

The impacts of aging and process variations on the performance of VLSI systems is increasing with each process generation. The conventional way to counteract them are extensive guard bands, which are calculated at system design time. Hence, they are necessarily worst case guard bands, i.e., most often too pessimistic. Current research tries to mitigate this by means of in-situ performance measurement based adaptive voltage scaling (AVS). The performance measurement is typically determined by means of dedicated sensors or canary logic. The parametrization of such AVS systems relies on assumptions regarding the relative behavior of the sensor and the application logic. Most published approaches use manually gained empirical data for this purpose. However, an automatic calibration procedure is needed for the practical application of these approaches. We propose such an automated calibration procedure and evaluate it on multiple FPGAs to consider the effects of aging and process variation. Furthermore, we use two designs to cover leakage power and dynamic power dominated scenarios. We achieve average power savings of 67% for a leakage dominated design and 48% for a test case with dominant dynamic power. Furthermore, we investigate the limitations of AVS systems regarding their capability to counteract fast disturbances, e.g., voltage drop.     

基于DVFS的移动通信终端省电方案

本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间.     

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhanced with an increase in the die temperature. The excessive timing slack observed in the clock period of subthreshold logic circuits at elevated temperatures provides opportunities to lower the active-mode energy consumption. A temperature-adaptive dynamic-supply voltage-tuning technique is proposed in this paper to reduce the high-temperature energy consumption without degrading the clock frequency in ultra-low-voltage subthreshold logic circuits. Results indicate that the energy consumption can be lowered by up to 40% by dynamically scaling the supply voltage at elevated temperatures. An alternative technique based on temperature-adaptive reverse body bias to exponentially reduce the subthreshold leakage currents at elevated temperatures is also investigated. The active-mode energy consumption with two temperature-adaptive voltage-tuning techniques is compared. The impact of the process parameter and supply voltage variations on the proposed temperature-adaptive voltage scaling techniques is evaluated.     

多路高压放大器输出直流电压监测与显示系统设计

在自适应光学系统中,自适应控制器AD输出控制信号需要通过高压放大器放大成高压电驱动压电陶瓷变形镜,从而实现波前实时校正.在实际系统中,往往需要对高压放大器输出电压进行实时监测.本系统采用小体积单片机C8051F310作为控制器,采用专用电表芯片CS5460A作为核心测量芯片,实现了单板对20路0～500 V直流电压的实时监测与显示,线性度优于0.2％.     

操作系统级低功耗动态电压缩放算法分析

低功耗的设计已经成为嵌入式系统设计中一个非常重要的方面，而动态电压调度（Dynamic Voltage Scaling DVS）又被认为是降低功耗的一种有效手段。本文对各类针对系统的动态电压缩放算法做了较系统的总结，给出了算法的模型，重点描述了操作系统级的两类动态电压缩放算法——基于间隔和基于任务的动态电压调度算法，概述了针对编译级的任务内动态电压调度算法。文章对三类算法作了分析与比较，由此给出了结论与观点，对以后动态电压缩放算法的研究做了预测。     

动态电压调整多处理器实时系统任务调度

动态电压调整DVS（Dynamic Voltage Scaling）是根据处理器电压（速度）降低之后，能量消耗平方级的减少这一原理提出的。文章通过DVS机制在多处理器实时系统中进行任务调度．通过对任务调度中的静态能量管理进行分析，在此基础上提出了一种新的基于DVS的适用于多处理器实时系统中的调度算法。这种新的调度算法是通过对贪婪法调度进行研究，发现其不足．并以此为基础进行改进。结合了动态电压调整的多处理器实时系统任务调度的能量消耗比普通的任务调度能量消耗有了很大的改善。     

A novel DC voltage control strategy of series hybrid active power filter

In this article, a novel DC voltage control strategy which is independent of the detection of the primary winding voltage across the series transformer is proposed to solve the DC voltage control problem of the series hybrid active power filter (APF). Meanwhile, this proposed DC voltage control method adopts an open-loop control strategy. The inverter generates unchanged DC voltage control current to ensure that the fundamental voltage loss of the series transformer remain stable. The simulation and experimental results validity and feasibility of the proposed DC voltage control the method of the series hybrid APF.     

Combining data remapping and voltage/frequency scaling of second level memory for energy reduction in embedded systems

In this paper we show that the energy reductions obtained from using two techniques, data remapping (DR) and voltage/frequency scaling of off-chip bus and memory, combine to provide interesting trade offs between energy, execution time and power. Both methods aim to reduce the energy consumed by the memory subsystem. DR is a fully automatic compile time technique applicable to pointer-intensive dynamic applications. Voltage/frequency scaling of off-chip memory is a technique applied at the hardware level. When combined together, energy reductions can be as high as 49.45%. The improvements are verified in the context of three OLDEN pointer-centric benchmarks, namely Perimeter, Health and TSP.     

基于小波基优化和动态比特分配的数字音频压缩编码方案

提出了一种新颖的基于自适应小波基优化选择和心理声学模型相结合的数字音频信号的透明质量编码方法，保证固定失真水平上使每帧信号的变换系数的动态分配的比特数最少，并且利用动态码本的方法来消除音频信号的统计冗余，进一步压缩比特率，对于抽样率为４４．１ｋＨｚ每样值用１６比特线性码表示的光盘单声道音乐信号可以压缩到６４ｋＢＰＳ左右。     

A digital predistortion assisted hybrid supply modulator for envelope tracking power amplifiers

In this paper, a novel digital predistortion assisted supply modulator is presented. The proposed modulator is suitable for envelope tracking power amplifiers. In this topology, a digitally controlled linear power amplifier is used to compensate the switching noise ripples of the switching modulator. The proposed structure is evaluated with a 0.18 µm CMOS process technology. The results show up to 9% static efficiency improvement in comparison with previous one-phase and two-phase architectures. It is shown that for a 5 MHz WiMAX signal with a 6.7 dB PAPR at 26.8 dBm output power, a maximum average efficiency of 73.5% is achieved in the proposed design.     

基于DVS的动态电压转换器设计

针对低功耗技术中的DVS(Dynamic Voltage Scaling)电路,本文介绍了一种动态电压转换器的设计。PWM(Pulse Width Modulation)控制电路是DC／DC转换器中的关键部件,重点介绍了一种新型可控占空比数字PWM控制电路的结构和工作原理,分析了这种数字PWM发生器的工作过程。该电路功耗低,所占面积小,适用于在动态功耗管理电路中的集成。     

Reference voltage calculation method based on zero-sequence component optimisation for a regional compensation DVR

This paper describes the design of a dynamic voltage restorer (DVR) that can simultaneously protect several sensitive loads from voltage sags in a region of an MV distribution network. A novel reference voltage calculation method based on zero-sequence voltage optimisation is proposed for this DVR to optimise cost-effectiveness in compensation of voltage sags with different characteristics in an ungrounded neutral system. Based on a detailed analysis of the characteristics of voltage sags caused by different types of faults and the effect of the wiring mode of the transformer on these characteristics, the optimisation target of the reference voltage calculation is presented with several constraints. The reference voltages under all types of voltage sags are calculated by optimising the zero-sequence component, which can reduce the degree of swell in the phase-to-ground voltage after compensation to the maximum extent and can improve the symmetry degree of the output voltages of the DVR, thereby effectively increasing the compensation ability. The validity and effectiveness of the proposed method are verified by simulation and experimental results.     

Virtual impedance control for a regional dynamic voltage restorer

A dynamic voltage restorer (DVR) can be installed in a middle-voltage (MV) power grid, to concurrently protect a cluster of sensitive loads from voltage sags. To further improve its efficiency and reduce the difficulty in its implementation, a novel control strategy for operating such a DVR as a virtual impedance in series with sensitive loads is proposed in this paper. In addition to its usual function of compensating for voltage sags, such a DVR can also operate as a virtual inductance, to function as a fault current limiter (FCL) during a downstream fault, or a virtual capacitance, to function as a series compensator (SC) to compensate the voltage loss along the feeder line during heavy load. Based on a dual-loop control design, strategies for operating a DVR as a series virtual inductance and a virtual capacitance are proposed, and methods for tuning the parameter values and a stability analysis of the whole system are presented. The feasibility and effectiveness of the proposed method are verified by simulations using the PSCAD software, and experimental results obtained using a prototype DVR are presented.     

一款宽供电电压范围工作的植入式神经信号记录前端芯片

摘要：本文设计了一款宽电压供电范围、用于神经电信号采集的前端芯片。该芯片主要由前端放大电路、仪表放大器（IA）和循环结构模数转换器（CADC）构成。在不采用分立元件的情况下,前端放大电路采用电容耦合、电容反馈的拓扑结构,结合伪电阻的应用,产生一个小于1Hz的-3dB高通频率截止点。双运算仪表放大器用于进一步提高增益的同时也为后续的模数转换电路提供一个较低的输出阻抗。前端放大电路和仪表放大电路共提供45.8dB的增益,其等效输入参考噪声电压为6.7uV从1Hz~5KHz积分）。放大后的信号被12位采样精度的ADC采样,该ADC最高采样速率为139KS/s,有效位数为8.7位。整个电路在1.34V到3.3V供电范围内消耗的总电流为165uA到 216uA。该芯片采用联华电子公司（UMC）的0.18-um 工艺制造,总面积1.06mm2 。该芯片在仿真生理环境下成功地记录到了神经电信号。